Silicon carbide semiconductor device integrating clamper circuit for clamping voltage
The present invention provides a silicon carbide (SiC) semiconductor device integrating a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bidirectional voltage clamping circuit. An object of protecting a device is achieved by using the simple structure above, effectively preventing device damage that may be caused by a positive overvoltage and a negative overvoltage between a gate and a source.
1. A silicon carbide (SiC) semiconductor device, integrating a damper circuit for clamping voltage, comprising:
a SiC substrate, comprising a first surface and a second surface opposite to the first surface;
an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET), comprising a SiC n-type drift layer, a gate, a source and a drain, wherein the SiC n-type drift layer, the gate and the source are disposed adjacent to the first surface and the drain is disposed adjacent to the second surface, the SiC n-type drift layer is provided with a plurality of p-type wells arranged at intervals, at least one p-type region disposed at the p-type well, at least one n-type region disposed at the p-type well, an insulator disposed on the SiC n-type drift layer, and a gate electrode connected to the gate; and
a bidirectional voltage clamp, disposed on the first surface, and comprising a first terminal connected to the gate and a second terminal connected to the source.
2. The SiC semiconductor device of claim 1 , wherein the bidirectional voltage clamp comprises at least one p-floating region spaced from the p-type well by a first distance, the p-floating region comprises a first n-type region and a second n-type region, the first n-type region and the second n-type region are separated from each other by a spacer region, the first terminal is connected to the gate electrode through an ohmic contact on the first n-type region, and the second terminal is connected to the source through an ohmic contact on the second n-type region.
3. The SiC semiconductor device of claim 2 , wherein between the first terminal and the spacer region is a second distance, between the second terminal and the spacer region is a third distance, and the second distance is greater than the third distance.
4. The SiC semiconductor device of claim 2 , wherein the p-floating region comprises a retrograde doping profile, in which the p-floating region comprises a bottom portion and a top portion comprising a doping concentration lower than that of the bottom portion.
5. The SiC semiconductor device of claim 1 , wherein the MOSFET is a planar MOSFET.
6. The SiC semiconductor device of claim 1 , wherein the MOSFET is a trench MOSFET.
7. The SiC semiconductor device of claim 1 , wherein the bidirectional voltage clamp suppresses a positive overvoltage and a negative overvoltage applied between the gate and the source.
8. The SiC semiconductor device of claim 7 , wherein absolute values of the positive overvoltage and the negative overvoltage are smaller than absolute values of positive and negative gate-to-source breakdown voltages of the MOSFET.
9. The SiC semiconductor device of claim 7 , wherein an absolute value of the positive overvoltage is greater than an absolute value of the negative overvoltage.
10. The SiC semiconductor device of claim 1 , wherein the bidirectional voltage clamp comprises a plurality of p-floating regions connected in parallel.