Address validation using signatures
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating signed addresses. One of the methods includes receiving, by a component from a device, a plurality of first requests, each first request for a physical address and including a virtual address, determining, by the component, a first physical address using the virtual address, generating a first signature for the first physical address, and providing, to the device, a response that includes the first signature, receiving, from the device, a plurality of second requests, each second request for access to a second physical address and including a second signature, determining, by the component for each of the plurality of second requests, whether the second physical address is valid using the second signature, and for each second request for which the second physical address is determined to be valid, servicing the corresponding second request.
1. A computer-implemented method comprising: receiving, by a component from a device, a request i) for data stored in a memory location in a memory storage and ii) including data in an address field and that has a first length and that references the memory location; extracting, from the data in the address field, address data that has a second length that is less than the first length, wherein the second length is selected as a number of bits required to address each memory location in the memory storage; extracting, from the data in the address field, a first signature that has a third length that is less than the first length, the first length being a sum of the second length and the third length; generating, using only the address data that has the second length, a second signature; determining whether the first signature is the same as the second signature; and in response to determining that the first signature is the same as the second signature, providing, by the component and to the device, data from the memory location, comprising: sending, by the component and to another component, a request for the data from the memory location;
receiving, by the component and from the other component, the data from the memory location; and providing, to the device, the data from the memory location.
2. The method of claim 1 , wherein:
receiving the request that includes the data in the address field and that has the first length comprises receiving the request that includes the data in the address field and that has a first quantity of bits;
extracting the address data that has the second length that is less than the first length comprises extracting the address data that has a second quantity of bits that is less than the first quantity of bits; and
extracting the first signature that has the third length that is less than the first length comprises extracting, from the data in the address field, the first signature that has a third quantity of bits that is less than the first quantity of bits, the first quantity of bits being a sum of the second quantity of bits and the third quantity of bits.
3. The method of claim 1 , wherein extracting the first signature comprises extracting leading data from the data in the address field.
4. The method of claim 1 , comprising:
receiving, by the component from the device, a request a) for access to the memory location with a physical address that has the first length and b) including a virtual address;
determining, by the component, the physical address using the virtual address;
generating a signature for the physical address, the signature for use to validate the physical address and having the third length that is less than the first length;
generating a shortened address that has the second length by removing, from the physical address, a quantity of data of the second length;
generating a response to the request that includes, in an address field, the signature appended to the shortened address; and
providing, to the device, the response that includes the signature appended to the shortened address, both in the address field.
5. The method of claim 4 , wherein generating the shortened address that has the second length comprises removing unnecessary data from the physical address.
6. The method of claim 4 , wherein:
receiving the request for access to the memory location with the physical address that has the first length comprises receiving the request for access to the memory location with the physical address that has a first quantity of bits;
generating the signature for the physical address comprises generating the signature for the physical address that has a second quantity of bits that is less than the first quantity of bits;
generating the shortened address comprises removing, from the physical address, the second quantity of bits; and
generating the response comprises generating the response that includes, in the address field that holds the first quantity of bits, the signature appended to the shortened address.
7. The method of claim 4 , wherein the address data comprises the shortened address.
8. The method of claim 1 , comprising:
decrypting the address data after extracting the address data from the data in the address field, wherein generating the second signature comprises generating, using the decrypted address data, the second signature.
9. A system comprising: a data processing apparatus; and a non-transitory computer readable storage medium in data communication with the data processing apparatus and storing instructions executable by the data processing apparatus and upon such execution cause the data processing apparatus to perform operations comprising: receiving, by a component from a device, a request i) for data stored in a memory location in a memory storage and ii) including data in an address field and that has a first length and that references the memory location; extracting, from the data in the address field, address data that has a second length that is less than the first length, wherein the second length is selected as a number of bits required to address each memory location in the memory storage; extracting, from the data in the address field, a first signature that has a third length that is less than the first length, the first length being a sum of the second length and the third length; generating, using only the address data that has the second length, a second signature; determining whether the first signature is the same as the second signature; and in response to determining that the first signature is the same as the second signature, providing, by the component and to the device, data from the memory location, comprising: sending, by the component and to another component, a request for the data from the memory location; receiving, by the component and from the other component, the data from the memory location; and providing, to the device, the data from the memory location.
10. The system of claim 9 , wherein:
receiving the request that includes the data in the address field and that has the first length comprises receiving the request that includes the data in the address field and that has a first quantity of bits;
extracting the address data that has the second length that is less than the first length comprises extracting the address data that has a second quantity of bits that is less than the first quantity of bits; and
extracting the first signature that has the third length that is less than the first length comprises extracting, from the data in the address field, the first signature that has a third quantity of bits that is less than the first quantity of bits, the first quantity of bits being a sum of the second quantity of bits and the third quantity of bits.
11. The system of claim 9 , wherein extracting the first signature comprises extracting leading data from the data in the address field.
12. The system of claim 9 , the operations comprising:
receiving, by the component from the device, a request a) for access to the memory location with a physical address that has the first length and b) including a virtual address;
determining, by the component, the physical address using the virtual address;
generating a signature for the physical address, the signature for use to validate the physical address and having the third length that is less than the first length;
generating a shortened address that has the second length by removing, from the physical address, a quantity of data of the second length;
generating a response to the request that includes, in an address field, the signature appended to the shortened address; and
providing, to the device, the response that includes the signature appended to the shortened address, both in the address field.
13. The system of claim 12 , wherein generating the shortened address that has the second length comprises removing unnecessary data from the physical address.
14. The system of claim 12 , wherein:
receiving the request for access to the memory location with the physical address that has the first length comprises receiving the request for access to the memory location with the physical address that has a first quantity of bits;
generating the signature for the physical address comprises generating the signature for the physical address that has a second quantity of bits that is less than the first quantity of bits;
generating the shortened address comprises removing, from the physical address, the second quantity of bits; and
generating the response comprises generating the response that includes, in the address field that holds the first quantity of bits, the signature appended to the shortened address.
15. The system of claim 12 , wherein the address data comprises the shortened address.
16. The system of claim 9 , comprising:
decrypting the address data after extracting the address data from the data in the address field, wherein generating the second signature comprises generating, using the decrypted address data, the second signature.
17. A non-transitory computer readable storage medium storing instructions executable by a data processing apparatus and upon such execution cause the data processing apparatus to perform operations comprising: receiving, by a component from a device, a request i) for data stored in a memory location in a memory storage and ii) including data in an address field and that has a first length and that references the memory location; extracting, from the data in the address field, address data that has a second length that is less than the first length, wherein the second length is selected as a number of bits required to address each memory location in the memory storage; extracting, from the data in the address field, a first signature that has a third length that is less than the first length, the first length being a sum of the second length and the third length; generating, using only the address data that has the second length, a second signature; determining whether the first signature is the same as the second signature; and in response to determining that the first signature is the same as the second signature, providing, by the component and to the device, data from the memory location, comprising: sending, by the component and to another component, a request for the data from the memory location; receiving, by the component and from the other component, the data from the memory location; and providing, to the device, the data from the memory location.
18. The computer readable storage medium of claim 17 , wherein:
receiving the request that includes the data in the address field and that has the first length comprises receiving the request that includes the data in the address field and that has a first quantity of bits;
extracting the address data that has the second length that is less than the first length comprises extracting the address data that has a second quantity of bits that is less than the first quantity of bits; and
extracting the first signature that has the third length that is less than the first length comprises extracting, from the data in the address field, the first signature that has a third quantity of bits that is less than the first quantity of bits, the first quantity of bits being a sum of the second quantity of bits and the third quantity of bits.