Out-of-band interrupt mapping in MIPI improved inter-integrated circuit communication
Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (I 2 C) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an I 2 C device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the I 2 C OBI, an I3C IBI that includes information related to the I 2 C OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.
1. An apparatus comprising:
an I3C bus;
a general purpose input-output (GPIO) pin to receive signals from an inter-integrated circuit (I 2 C) device;
processing circuitry coupled to the I3C bus and to the GPIO pin to:
identify an out-of-band interrupt (OBI) received via the GPIO pin;
generate an I3C in-band interrupt (IBI) that includes an address of the I 2 C device, wherein one or more high-ordered bits of the address are inverted.
2. The apparatus of claim 1 , further comprising:
transmission circuitry coupled with the processing circuitry, the transmission circuitry to transmit the I3C IBI on the I3C bus.
3. The apparatus of claim 1 , wherein the I 2 C device is unable to directly generate an I3C IBI for consumption by the one or more I3C devices coupled to the I3C bus.
4. The apparatus of claim 1 , wherein the inversion of the high-ordered bits is to avoid conflict on the I3C bus.
5. The apparatus of claim 1 , wherein the processing circuitry is further to interrogate the I 2 C device for information related to the identified OBI.
6. The apparatus of claim 5 , wherein the processing circuitry is further to interrogate the I 2 C device via the I3C bus.
7. A method for implementing a host controller, the method comprising:
receiving an OBI from an I 2 C device via a GPIO pin;
generating an I3C IBI that includes an address of the I 2 C device that has a most significant bit (MSb) different than a MSb of an address of another I3C device; and
transmitting the I3C IBI on an I3C bus.
8. The method of claim 7 , wherein the I 2 C device is unable to directly generate the I3C IBI for consumption by one or more I3C devices coupled to the I3C bus.
9. The method of claim 7 , further comprising interrogating the I 2 C device for information related to the received OBI.
10. The method of claim 7 , further comprising interrogating the I 2 C device via the I3C bus to determine a cause of the interrupt.
11. The method of claim 7 , further comprising clearing an interrupt on the GPIO pin.
12. A computing device, comprising:
an I3C bus;
processing circuitry to couple with the I3C bus and with a general purpose input-output (GPIO) pin, the GPIO pin to receive signals from an inter-integrated circuit (I 2 C) device,
wherein the processing circuitry is to:
identify an address of the I 2 C device based on a received out-of-band interrupt (OBI) signal received from the I 2 C device;
transform the identified address of the I 2 C device by setting a most significant bit (MSb) of the identified address for transmission on the I3C bus to one; and
generate an in-band interrupt (IBI) signal for the I3C bus based upon the transformed address and the received OBI signal.
13. The computing device of claim 12 , wherein the computing device is a mobile device.
14. The computing system of claim 12 , wherein the processing circuitry is further to transmit the generated IBI signal on the I3C bus to I 2 C devices or I3C devices.
15. The computing system of claim 12 , wherein setting the MSb of the identified address for transmission on the I3C bus to one is to avoid a conflict on the I3C bus.
16. The computing system of claim 12 , wherein the processing circuitry is further to interrogate the I 2 C device via the I3C bus to determine a cause of the interrupt.
17. The computing system of claim 12 , wherein the processing circuitry is further to clear an interrupt on the GPIO pin.