MRAM integration with BEOL interconnect including top via

1. A method for preventing excessive cap dielectric loss in memory areas and logic areas of a device, the method comprising:

forming a U-shaped conductive line and a conductive pad in direct contact with a dielectric layer, wherein the conductive line defines dual top vias and the conductive pad includes a microstud, and wherein an entire bottom surface of the U-shaped conductive line directly contacts a top surface of the dielectric layer;

depositing a dielectric cap in direct contact with a top surface of the U-shaped conductive line defined between the dual top vias, and with a portion of a top surface of the conductive pad; and

constructing a top electrode, a magnetic tunnel junction (MTJ) stack, and a bottom electrode in vertical alignment with the microstud of the conductive pad.

2. The method of claim 1 , further comprising depositing an encapsulation layer.

3. The method of claim 2 , further comprising recessing the encapsulation layer to expose an upper area of the top electrode.

4. The method of claim 3 , further comprising depositing an inter-layer dielectric (ILD).

5. The method of claim 4 , further comprising forming first top metal lines with a first set of vias connecting to the top via above the U-shaped conductive line and a second top metal line connecting to the top electrode, wherein the first top metal lines with the first set of vias and the second top metal line are filled with a conductive material.

6. The method of claim 5 , wherein the U-shaped conductive line with the top via reduces a length of the first set of vias, and thicker dielectric above the U-shaped conductive line and the conductive pad prevents excess gouging of the dielectric cap.

7. The method of claim 1 , wherein the U-shaped conductive line is vertically offset from the conductive pad.

8. The method of claim 1 , wherein the conductive pad with the microstud has a substantially inverted T-shaped configuration.

9. The method of claim 1 , wherein the microstud of the conductive pad directly contacts the bottom electrode.

10. The method of claim 1 , wherein the U-shaped conductive line and the conductive pad include ruthenium (Ru).

11. A method for reducing gouging of a dielectric cap by employing a subtractive etch technique forming a top via, the method comprising:

forming a U-shaped conductive line defining dual top vias in a logic area of a device, wherein an entire bottom surface of the U-shaped conductive line directly contacts a top surface of a dielectric layer;

forming a conductive pad with a microstud in a memory area of the device;

depositing a dielectric cap in direct contact with a top surface of the U-shaped conductive line defined between the dual top vias, and with a portion of a top surface of the conductive pad;

constructing MRAM pillars in the memory area, wherein the MRAM pillars are in direct contact with the microstud above the conductive pad;

encapsulating the MRAM pillars with an encapsulation layer;

recessing the encapsulation layer to expose an upper area of the MRAM pillars; and

forming metal lines to a top section of the MRAM pillars and metal lines with vias to a top surface of the top via above the U-shaped conductive line.

12. The method of claim 11 , wherein each of the MRAM pillars includes a top electrode, a magnetic tunnel junction (MTJ) stack, and a bottom electrode.

13. The method of claim 12 , wherein the U-shaped conductive line is vertically offset from the conductive pad.

14. The method of claim 13 , wherein the conductive pad with the microstud has a substantially inverted T-shaped configuration.

15. The method of claim 11 , wherein the microstud of the conductive pad directly contacts a bottom electrode.

16. The method of claim 11 , wherein the U-shaped conductive line and the conductive pad include ruthenium (Ru).