Nanosheet field-effect transistor device and method of forming

1. A semiconductor device comprising:

a fin protruding above a substrate;

source/drain regions over the fin;

nanosheets between the source/drain regions, wherein the nanosheets comprise a first semiconductor material;

inner spacers between the nanosheets and at opposite ends of the nanosheets, wherein there is an air gap between each of the inner spacers and a respective source/drain region of the source/drain regions;

a material layer between each of the inner spacers and the respective source/drain region, wherein the air gap is between each of the inner spacers and the material layer, wherein the source/drain regions have a plurality of protrusions extending between the nanosheets toward the inner spacers, wherein the material layer extends conformally over the plurality of protrusions; and

a gate structure over the fin and between the source/drain regions.

2. The semiconductor device of claim 1 , wherein the nanosheets are parallel to each other and are parallel to a major upper surface of the substrate.

3. The semiconductor device of claim 1 , wherein the material layer is a layer of a second semiconductor material.

4. The semiconductor device of claim 3 , wherein the first semiconductor material is a same as the second semiconductor material.

5. The semiconductor device of claim 1 , wherein the material layer is a layer of a first dielectric material, and the inner spacers comprise a second dielectric material.

6. The semiconductor device of claim 5 , wherein the first dielectric material is a same as the second dielectric material.

7. The semiconductor device of claim 1 , wherein the air gap is sealed in a space between each of the inner spacers and the respective source/drain region, and between adjacent ones of the nanosheets.

8. The semiconductor device of claim 1 , wherein each of the inner spacers has a concave surface facing the gate structure.

9. The semiconductor device of claim 8 , wherein each of the inner spacers has another concave surface facing the source/drain regions.

10. The semiconductor device of claim 1 , wherein each of the inner spacers is a single-material layer.

11. The semiconductor device of claim 1 , wherein the air gap has a width between each of the inner spacers and the material layer, where the width increases continuously along a direction from a center of two adjacent nanosheets toward one of the two adjacent nanosheets.

12. A semiconductor device comprising:

a fin protruding above a substrate;

a gate structure over the fin;

source/drain regions over the fin on opposing sides of the gate structure;

a first channel layer and a second channel layer disposed between the source/drain regions and parallel to each other, wherein the gate structure wraps around the first channel layer and the second channel layer; and

inner spacers disposed between end portions of the first channel layer and end portions of the second channel layer, wherein there are air gaps between the inner spacers and the source/drain regions, wherein each of the inner spacers has a first concave surface facing the gate structure, and has a second concave surface facing the source/drain regions.

13. The semiconductor device of claim 12 , further comprising a material layer between the inner spacers and the source/drain regions, wherein the air gaps are between the inner spacers and the material layer.

14. The semiconductor device of claim 13 , wherein the material layer is semiconductor layer.

15. The semiconductor device of claim 13 , wherein the material layer is a dielectric layer.

16. The semiconductor device of claim 15 , wherein the inner spacers and the material layer comprise a same dielectric material.

17. A method of forming a semiconductor device, the method comprising:

forming a dummy gate structure over a nanostructure and over a fin, the nanostructure overlying the fin, the fin protruding above a substrate, the nanostructure comprising alternating layers of a first semiconductor material and a second semiconductor material;

forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material;

recessing the exposed end portions of the first semiconductor material to form recesses;

forming dummy inner spacers in the recesses and a material layer over the dummy inner spacers in the recesses;

forming source/drain regions in the openings after forming the material layer;

after forming the source/drain regions, removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material disposed under the dummy gate structure;

removing the exposed first semiconductor material and the dummy inner spacers, wherein the second semiconductor material remain and form a plurality of nanosheets, wherein the material layer is exposed after removing the dummy inner spacers; and

forming inner spacers between the source/drain regions at opposite ends of the plurality of nanosheets, wherein each of the inner spacers seals an air gap between the each of the inner spacers and the material layer.

18. The method of claim 17 , further comprising after forming the inner spacers, forming a replacement gate structure that wraps around the plurality of nanosheets.

19. The method of claim 17 , wherein forming the material layer comprises forming the material layer using a semiconductor material.

20. The method of claim 17 , wherein forming the material layer comprises forming the material layer using a dielectric material.