IP Library Granted Patent US 11,230,779
Granted Patent B2
US 11,230,779 · App. 16/880,091 · Granted Jan 25, 2022

Substrate plating method

Inventor: Katsuya Kubo (Nagano, JP)
Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
C25D3/38C25D5/022H05K3/188
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Quick Facts
Patent No.
US 11,230,779
App. No.
16/880,091
Granted
Jan 25, 2022
Kind
B2
Abstract

A substrate plating method includes forming a first resist film exposing a first feeding layer on a first face of a substrate; forming a second resist film exposing a second feeding layer on a second face of the substrate opposite to the first face; holding the substrate with a clamp member in such a manner that the clamp member is in contact with the first feeding layer and the second feeding layer, and arranging a first electrode in opposed relation with the first face and a second electrode in opposed relation with the second face; and forming a plating layer on a plating-scheduled region of the first face under conditions in which a value of current supplied between the second face and the second electrode is larger than a value of current supplied between the first face and the first electrode.

Claims (11)

1. A substrate plating method comprising:

forming a first resist film on a first face of a substrate in such a manner that the first resist film has an opening on a plating-scheduled region of the first face and exposes a first feeding layer in at least a portion of an outer edge of the first face;

forming a second resist film on a second face of the substrate opposite to the first face in such a manner that the second resist film exposes a second feeding layer in at least a portion of an outer edge of the second face;

holding the substrate with a clamp member in such a manner that the clamp member is in contact with the first feeding layer and the second feeding layer, and arranging a first electrode in opposed relation with the first face of the substrate and a second electrode in opposed relation with the second face of the substrate; and

forming a plating layer on the plating-scheduled region of the first face while using the first resist film as a mask under conditions in which a value of current supplied between the second face of the substrate and the second electrode is larger than a value of current supplied between the first face of the substrate and the first electrode.

2. The substrate plating method according to claim 1 , wherein the second resist film has a C-shaped cutout that is disposed at a location corresponding to complete periphery of the outer edge of the second face, and that exposes the second feeding layer.

3. The substrate plating method according to claim 1 , wherein the second resist film has an L-shaped cutout that is disposed, on the outer edge of the second face, at a location corresponding to a portion along one side of the second face that is to be intersected by the clamp member and along other two sides that are continuous to the one side, and that exposes the second feeding layer.

4. The substrate plating method according to claim 1 , wherein the value of current supplied between the first face of the substrate and the first electrode is set at 5 to 10 A, and the value of current supplied between the second face of the substrate and the second electrode is set at 7.5 to 20 A.

5. The substrate plating method according to claim 1 , wherein a ratio of the value of current supplied between the second face of the substrate and the second electrode to the value of current supplied between the first face of the substrate and the first electrode is in a range of 1.5 to 3.

6. The substrate plating method according to claim 1 , wherein the second resist film has an opening only in a portion of an outer edge of the second face.

7. The substrate plating method according to claim 1 , wherein the substrate has a rectangular shape in plan view, and the holding includes holding each of two opposed shorter sides of the rectangular shape with the clamp member.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 21, 2020
From: KUBO, KATSUYA
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 052724/0229 →
Priority Claims (1)
JP JP2019-102986 · May 31, 2019 · national
Continuity (1)
Related Publication 20200378026A1 · Dec 3, 2020