Semiconductor device and method of fabricating the same
A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.
1. A semiconductor device, comprising:
a semiconductor substrate that includes a trench defining an active region;
a buried dielectric pattern in the trench;
a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and
a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench,
wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer,
wherein the second surface includes a plurality of silicon grains that are uniformly distributed, and
wherein the polycrystalline silicon layer is prepared by:
performing a deposition process at a first temperature range to form an amorphous silicon layer on a surface of the semiconductor substrate including directly on inner walls of the trench; and
performing a rapid thermal annealing process on the amorphous silicon layer at a second temperature range while providing H 2 O, O 2 ,O 3 , or oxygen radicals on a surface of the amorphous silicon layer to form the polycrystalline silicon layer, the second temperature range being different from the first temperature range.
2. The device as claimed in claim 1 , wherein a surface roughness of the second surface is substantially the same as a surface roughness of the first surface.
3. The device as claimed in claim 1 , wherein the second surface has a surface roughness of 0.1 Å to 10 Å.
4. The device as claimed in claim 1 , wherein:
the semiconductor substrate includes a single crystalline silicon substrate, and
the polycrystalline silicon layer is in direct contact with the single crystalline silicon substrate.
5. The device as claimed in claim 1 , wherein the silicon oxide layer is thicker than the polycrystalline silicon layer when measured in a same direction.
6. The device as claimed in claim 1 , further comprising a discontinuous native oxide layer that is locally positioned between the semiconductor substrate and the first surface of the polycrystalline silicon layer.
7. The device as claimed in claim 1 , wherein a width of the active region is less than a width of the trench.
8. The device as claimed in claim 1 , wherein:
the polycrystalline silicon layer extends along a sidewall of the trench toward a top surface of the semiconductor substrate, and
the polycrystalline silicon layer has a first thickness on the sidewall of the trench and a second thickness on the top surface of the semiconductor substrate, the second thickness being different from the first thickness.
9. A semiconductor device, comprising:
a semiconductor substrate that includes a trench defining an active region;
a buried dielectric pattern in the trench;
a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench;
a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench;
a conductive line that is in the semiconductor substrate and runs across the active region;
a gate dielectric layer between the semiconductor substrate and the conductive line; and
a plurality of impurity regions in the active region on opposite sides of the conductive line,
wherein the polycrystalline silicon layer has a first surface in contact with the silicon oxide layer, and
wherein the first surface includes a plurality of silicon grains that are uniformly distributed, and
wherein the polycrystalline silicon layer is prepared by:
performing a deposition process at a first temperature range to form an amorphous silicon layer on a surface of the semiconductor substrate including directly on inner walls of the trench; and
performing a rapid thermal annealing process on the amorphous silicon layer at a second temperature range while providing H 2 O, O 2 , O 3 , or oxygen radicals on a surface of the amorphous silicon layer to form the polycrystalline silicon layer, the second temperature range being different from the first temperature range.
10. The device as claimed in claim 9 , wherein the polycrystalline silicon layer is in contact with a bottom surface of the trench and a portion of a lateral surface of the trench.
11. The device as claimed in claim 9 , wherein:
the semiconductor substrate includes a single crystalline silicon substrate, and
the polycrystalline silicon layer is in direct contact with the single crystalline silicon substrate.
12. The device as claimed in claim 9 , wherein the gate dielectric layer is in contact with a portion of the polycrystalline silicon layer and a portion of the silicon oxide layer.
13. The device as claimed in claim 9 , wherein the first surface of the polycrystalline silicon layer has a surface roughness of 0.1 Å to 10 Å.
14. The device as claimed in claim 9 , wherein the silicon oxide layer is thicker than the polycrystalline silicon layer when measured in a same direction.
15. The device as claimed in claim 9 , wherein a width of the active region is less than a width of the trench.