Semiconductor device package and method of manufacturing the same
A semiconductor device package includes a dielectric layer, a package body and a protection structure. The dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The package body is disposed on the first surface of the dielectric layer. The package body covers a first portion of the lateral surface of the dielectric layer and exposes a second portion of the lateral surface of the dielectric layer. The protection structure is disposed on the second portion of the lateral surface of the dielectric layer.
1. A semiconductor device package, comprising:
a dielectric layer having a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface;
a package body disposed on the first surface of the dielectric layer, the package body covering a first portion of the lateral surface of the dielectric layer and exposing a second portion of the lateral surface of the dielectric layer; and
a protection structure disposed on the second portion of the lateral surface of the dielectric layer,
wherein a lateral surface of the protection structure is covered by the package body.
2. The semiconductor device package of claim 1 , wherein the package body has a surface between the first surface and the second surface of the dielectric layer.
3. The semiconductor device package of claim 2 , wherein the protection structure is disposed on the surface of the package body.
4. The semiconductor device package of claim 1 , wherein a lateral surface of the protection structure is covered by the package body.
5. The semiconductor device package of claim 1 , wherein a material of the protection structure is different from a material of the package body and a material of the dielectric layer.
6. The semiconductor device package of claim 1 , further comprising:
an interconnection layer disposed within the dielectric layer;
a first conductive via within the dielectric layer and electrically connected to the interconnection layer; and
a second conductive via within the dielectric layer and on the first conductive via.
7. The semiconductor device package of claim 6 , further comprising a seed layer disposed between the first conductive via and the second conductive via.
8. The semiconductor device package of claim 1 , further comprising an electronic component disposed on the first surface of the dielectric layer and encapsulated by the package body.
9. A semiconductor device package, comprising:
a circuit layer having an interconnection layer and a dielectric layer covering the interconnection layer, the circuit layer having a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface;
an electronic component disposed on the first surface of the circuit layer and electrically connected to the interconnection layer;
a package body disposed on the first surface of the circuit layer and covering the electronic component; and
a protection structure in contact with the circuit layer,
wherein the lateral surface of the circuit layer is recessed from a lateral surface of the package body, and
wherein the protection structure has a surface substantially coplanar with the second surface of the circuit layer.
10. The semiconductor device package of claim 9 , wherein the package body covers a first portion of the lateral surface of the circuit layer and exposes a second portion of the circuit layer.
11. The semiconductor device package of claim 10 , wherein the package body has a surface between the first surface and the second surface of the circuit layer.
12. The semiconductor device package of claim 9 , wherein the package body has a surface substantially coplanar with the second surface of the circuit layer.
13. The semiconductor device package of claim 9 , wherein a material of the protection structure is different from a material of the package body and a material of the dielectric layer.
14. The semiconductor device package of claim 9 , further comprising:
a first conductive via within the dielectric layer and electrically connected to the interconnection layer; and
a second conductive via within the dielectric layer and on the first conductive via.
15. The semiconductor device package of claim 14 , further comprising a seed layer disposed between the first conductive via and the second conductive via.
16. The semiconductor device package of claim 8 , further comprising an underfill disposed between the dielectric layer and the electronic component.
17. The semiconductor device package of claim 9 , further comprising an underfill disposed between the circuit layer and the electronic component.