Neuromorphic computing device
A neuromorphic computing device includes synapse weights. The synapse weights have different weight values resulted from different transistor arrangements of the synapse weights.
1. A neuromorphic computing device, comprising:
synapse weights having different weight values which results from different transistor arrangements of the synapse weights.
2. The neuromorphic computing device according to claim 1 , wherein each of the synapse weights has at least one active transistor and/or at least one dummy transistor.
3. The neuromorphic computing device according to claim 2 , wherein the synapse weights have different amounts of active transistor.
4. The neuromorphic computing device according to claim 2 , wherein each of the active transistor and the dummy transistor comprises:
a substrate;
a source;
a drain; and
a gate on the semiconductor substrate between the source and the drain.
5. The neuromorphic computing device according to claim 1 , wherein the synapse weights have the same amount of transistor.
6. The neuromorphic computing device according to claim 1 , wherein one of the synapse weights has a dummy transistor.
7. The neuromorphic computing device according to claim 6 , wherein the dummy transistor has a source/drain being floating.
8. The neuromorphic computing device according to claim 1 , further comprising:
a first neural circuit; and
a second neural circuit,
wherein one of the synapse weights has an active transistor electrically connected between the first neural circuit and the second neural circuit.
9. The neuromorphic computing device according to claim 1 , further comprising a first neural circuit electrically connected to sources/drains of transistors of the synapse weights, wherein the transistors electrically connected to the first neural circuit have a common gate.
10. The neuromorphic computing device according to claim 1 , further comprising a second neural circuit electrically connected to sources/drains of transistors of the synapse weights, wherein the transistors electrically connected to the second neural circuit have gates separated from each other.
11. The neuromorphic computing device according to claim 1 , wherein one synapse weight of the synapse weights comprises at least one transistor and at least one first conductive element electrically connected onto a source/drain of the at least one transistor.
12. The neuromorphic computing device according to claim 11 , wherein the at least one first conductive element is functioned as a signal input element of the one synapse weight.
13. The neuromorphic computing device according to claim 12 , further comprising a first neural circuit, wherein the first neural circuit comprises a first conductive layer disposed on the at least one first conductive element, the at least one first conductive element is electrically connected between the first conductive layer and the source/drain.
14. The neuromorphic computing device according to claim 11 , wherein the at least one first conductive element is used as a signal output element of the one synapse weights.
15. The neuromorphic computing device according to claim 14 , further comprising:
a first conductive layer disposed on the at least one first conductive element;
a second conductive element disposed on the first conductive layer;
a second conductive layer disposed on the second conductive element;
a third conductive element disposed on the second conductive layer; and
a third conductive layer disposed on the third conductive element;
wherein the at least one first conductive element, the first conductive layer, the second conductive element, the second conductive layer and the third conductive element are electrically connected between the third conductive layer and the source/drain.
16. The neuromorphic computing device according to claim 15 , comprising a second neural circuit, wherein the second neural circuit comprises the second conductive layer, the third conductive element and the third conductive layer.
17. The neuromorphic computing device according to claim 11 , wherein each of the transistors comprises an another source/drain, wherein the source/drain is one of a source and a drain, the another source/drain is the other of the source and the drain, the synapse weights have a signal output element electrically connected to the another source/drain of at least one of the transistors.
18. The neuromorphic computing device according to claim 1 , wherein the synapse weights have transistors having a common gate, or having a common source/drain.
19. The neuromorphic computing device according to claim 1 , wherein one of the synapse weights has transistors having a common gate, or having a common source/drain.
20. The neuromorphic computing device according to claim 1 , wherein the synapse weights have transistors having different doping arrangements.
21. The neuromorphic computing device according to claim 1 , wherein the weight values are defined by using a photomask directly.