Single flux quantum circuit that includes a sequencing circuit
A single flux quantum (SFQ) circuit can include a combinational logic network, which can include a set of SFQ logic cells. The SFQ circuit can also include an SFQ sequencing circuit, which can be used to generate delayed versions of clock pulses to clock the set of SFQ logic cells.
1. A circuit, comprising:
a single flux quantum (SFQ) combinational logic network comprising a set of SFQ logic cells;
an SFQ sequencing circuit to generate delayed versions of clock pulses to clock the set of SFQ logic cells; and
a set of SFQ flip-flop cells, wherein an output of at least on SFQ flip-flop cell in the set of SFQ flip-flop cells is coupled to an input of at least one SFQ logic cell in the set of SFQ logic cells.
2. The circuit of claim 1 , wherein each SFQ flip-flop cell in the set of SFQ flip-flop cells is assigned a level value of zero, and wherein each SFQ logic cell in the set of SFQ logic cells is assigned a level value that is one greater than a maximum level value of SFQ flip-flop cells or SFQ logic cells that are coupled to inputs of the SFQ logic cell.
3. The circuit of claim 2 , wherein the SFQ sequencing circuit comprises a series of SFQ delay sub-circuits, wherein each SFQ delay sub-circuit corresponds to a specific level value.
4. The circuit of claim 3 , wherein each SFQ delay sub-circuit comprises a Josephson transmission line (JTL) and a splitter sub-circuit comprising one or more splitters.
5. The circuit of claim 3 , wherein each SFQ delay sub-circuit comprises a SFQ flip-flop and a splitter sub-circuit comprising one or more splitters.
6. The circuit of claim 3 , wherein at least one SFQ delay sub-circuit clocks SFQ logic cells in multiple SFQ combinational logic networks.
7. The circuit of claim 1 , wherein at least one SFQ logic cell in the set of SFQ logic cells comprises at least one Josephson junction biased using a Josephson junction based current source.
8. The circuit of claim 1 , wherein at least one SFQ logic cell in the set of SFQ logic cells comprises a Josephson junction, wherein an output terminal of the SFQ logic cell is coupled to a terminal of the Josephson junction through a termination resistance and a superconducting inductor.
9. A circuit, comprising:
a set of single flux quantum (SFQ) flip-flop cells;
a set of SFQ combinational logic networks, each SFQ combinational logic network comprising a set of SFQ logic cells;
wherein an output of at least one SFQ flip-flop cell is coupled to an input of at least one SFQ logic cell; and
wherein delayed versions of clock pulses are provided to SFQ logic cells in the set of SFQ combinational logic networks.
10. The circuit of claim 9 , wherein each SFQ flip-flop cell is assigned a level value of zero, and wherein each SFQ logic cell is assigned a level value that is one greater than a maximum level value of SFQ flip-flop cells or SFQ logic cells that are coupled to inputs of the SFQ logic cell.
11. The circuit of claim 10 , comprising an SFQ sequencing circuit to generate the delayed versions of the clock pulses.
12. The circuit of claim 11 , wherein the SFQ sequencing circuit comprises a series of SFQ delay sub-circuits, wherein each SFQ delay sub-circuit corresponds to a specific level value.
13. The circuit of claim 12 , wherein each SFQ delay sub-circuit comprises a Josephson transmission line (JTL) and a splitter sub-circuit comprising one or more splitters.
14. The circuit of claim 12 , wherein each SFQ delay sub-circuit comprises a SFQ flip-flop and a splitter sub-circuit comprising one or more splitters.
15. The circuit of claim 9 , wherein at least one SFQ logic cell comprises at least one Josephson junction biased using a Josephson junction based current source.
16. The circuit of claim 9 , wherein at least one SFQ logic cell comprises a Josephson junction, wherein an output terminal of the SFQ logic cell is coupled to a terminal of the Josephson junction through a termination resistance and a superconducting inductor.
17. A circuit, comprising:
a single flux quantum (SFQ) combinational logic network comprising SFQ logic cells coupled using superconducting stripline structures; and
an SFQ sequencing circuit to generate delayed versions of clock pulses to clock the SFQ logic cells.
18. The circuit of claim 17 , wherein at least one SFQ logic cell comprises at least one Josephson junction biased using a Josephson junction based current source, wherein the Josephson junction based current source comprises a Josephson junction.
19. The circuit of claim 17 , wherein at least one SFQ logic cell comprises a Josephson junction, wherein an output terminal of the SFQ logic cell is coupled to a terminal of the Josephson junction through a termination resistance and a superconducting inductor.