Frequency estimation
A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.
1. A frequency estimator for estimating a frequency of a signal, comprising:
a counter configured to count an integer number of full clock cycles of the signal during a measurement time window;
a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle of the signal during the measurement time window;
a synchronizer configured to generate an enable synchronization signal by shifting an edge timing of an enable signal derived from a reference clock to correlate with an edge timing of the frequency to be estimated, wherein the enable synchronization signal defines the measurement time window; and
a processor configured to determine the estimated frequency of the signal based on the counted number of full clock cycles and the measured fraction of the clock cycle.
2. The frequency estimator of claim 1 , wherein the TDC is configured to measure a time difference between the enable signal and the enable synchronization signal.
3. The frequency estimator of claim 2 , wherein the TDC comprises:
a first TDC configured to measure a first time difference between a start of the enable signal and a start of the enable synchronization signal; and
a second TDC configured to measure a second time difference between an end of the enable signal and an end of the enable synchronization signal,
wherein a difference between the second time difference and the first time difference is the time difference between the enable signal and the enable synchronization signal.
4. The frequency estimator of claim 3 , wherein the processor is configured to determine the estimated frequency to be the integer number of full clock cycles, plus the first time difference, minus the second time difference.
5. The frequency estimator of claim 3 , wherein the processor is configured to determine the estimated frequency based on
f
~
RF
=
K
N
/
f
ref
-
ɛ
1
+
ɛ
2
,
where K is the integer number of counted full clock cycles during the measurement time window, f ref is a reference frequency of the reference clock, and N is a number of full clock cycles of the reference clock during the measurement time window, ε 1 is the first time difference, and ε 2 is the second time difference.
6. The frequency estimator of claim 1 , wherein the processor is configured to determine the estimated frequency based on
f
~
RF
=
(
K
+
P
)
·
f
ref
N
,
where K is the integer number of counted full clock cycles during the measurement time window, P is the measured fraction of the clock cycle during the measurement time window, f ref is a reference frequency of the reference clock, and N is a number of full clock cycles of the reference clock during the measurement time window.
7. A Voltage Controlled Oscillator (VCO) comprising the frequency estimator of claim 1 .
8. A Phase Locked Loop (PLL) comprising the frequency estimator of claim 1 .
9. A method of estimating a frequency of a signal, comprising:
counting, by a counter, an integer number of full clock cycles of the signal during a measurement time window;
measuring, by a Time-to-Digital Converter (TDC), a fraction of a clock cycle during the measurement time window;
generating, by a synchronizer, an enable synchronization signal by shifting an edge timing of an enable signal derived from a reference clock to correlate with an edge timing of the frequency to be measure, wherein the enable synchronization signal defines the measurement time window; and
determining, by a processor, the estimated frequency of the signal based on the counted number of full clock cycles and the measured fraction of the clock cycle.
10. The method of claim 9 , wherein the measuring of the fraction of the clock cycle comprises measuring a time difference between the enable signal and the enable synchronization signal.
11. The method of claim 10 , wherein the measuring of the fraction of the clock cycle comprises:
measuring, by a first TDC, a first time difference between a start of the enable signal and a start of the enable synchronization signal; and
measuring, by a second TDC, a second time difference between an end of the enable signal and an end of the enable synchronization signal,
wherein a difference between the second time difference and the first time difference is the time difference between the enable signal and the enable synchronization signal.
12. The method of claim 11 , wherein the determining the estimated frequency is based on the integer number of full clock cycles, plus the first time difference, minus the second time difference.
13. The method of claim 11 , wherein the determining the estimated frequency is based on
f
~
RF
=
K
N
/
f
ref
-
ɛ
1
+
ɛ
2
,
where K is the integer number of counted full clock cycles during the measurement time window, f ref is a reference frequency of the reference clock, and N is a number of full clock cycles of the reference clock during the measurement time window, ε 1 is the first time difference, and ε 2 is the second time difference.
14. The method of claim 9 , wherein the determining the estimated frequency based on
f
~
RF
=
(
K
+
P
)
·
f
ref
N
,
where K is the integer number of counted full clock cycles during the measurement time window, P is the measured fraction of the clock cycle during the measurement time window, f ref is a reference frequency of the reference clock, and N is a number of full clock cycles of the reference clock during the measurement time window.