Current control for a multicore processor
Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.
1. An integrated circuit comprising:
a first current comparator and a second current comparator coupled to a first processor core of a plurality of processor cores, the first current comparator is to indicate whether a current measurement of the first processor core exceeds a first threshold and the second current comparator is to indicate whether the current utilization measurement of the first processor core exceeds a second threshold which is lower than the first threshold; and
control circuitry to:
determine to throttle the first processor core based on an indication received from the first current comparator that the current measurement of the first processor core exceeds the first threshold;
track a number of times the current measurement of the first processor core exceeds the second threshold based on indications received from the second current comparator that the current measurement of the first processor core exceeds the second threshold; and
determine whether to change an allocation of a power budget for the first processor core based on the count.
2. The integrated circuit of claim 1 , wherein the first current comparator and the second current comparator are to receive the current measurement from the first processor core.
3. The integrated circuit of claim 1 , wherein the control circuitry is further to:
receive one or more updated indications from the first current comparator;
determine to release the throttling of the first processor core based on the one or more updated indications; and
send a throttle release request to the first processor core based on the determination to release the throttling.
4. The integrated circuit of claim 3 , wherein the determination to release the throttling is based further a historical log of indications for the first processor core.
5. The integrated circuit of claim 1 , wherein the indication received from the first current comparator that the current measurement of the first processor core exceeds the first threshold is a first indication, the control circuitry is further to receive one or more prior indications prior to the first indication, and the determination to throttle is based further on the one or more prior indications.
6. The integrated circuit of claim 1 , wherein the control circuitry includes a power control unit (PCU) to individually set respective voltages of the plurality of processor cores.
7. The integrated circuit of claim 6 , further comprising voltage regulator circuitry coupled to the plurality of processor cores, the voltage regulator circuitry to provide the individually set voltages to the plurality of processor cores in response to a command from the PCU.
8. The integrated circuit of claim 1 , wherein to change the allocation of the power budget of the first processor core, the control circuitry is to lower the first threshold.
9. The integrated circuit of claim 1 , wherein the control circuitry is to increase a current threshold used to determine whether to throttle another processor core of the plurality of processor cores when the first threshold is lowered for the first processor core.
10. One or more non-transitory computer-readable media (NTCRM) having instructions, stored thereon, that when executed by circuitry of a multicore processor cause the circuitry to:
receive one or more current utilization measurements for respective ones of a plurality of cores of the multicore processor, the one or more current utilization measurements include one or more current utilization measurements for a first core of the plurality of cores;
determine to throttle the first core based on the one or more current utilization measurements for the first core exceeding a threshold and to release throttling of the first core based on the one or more current utilization measurements for the first core returning to within the threshold; and
determine whether to change an allocation of a power budget for the first core based on a frequency of the throttling and releasing of the throttling of the first core.
11. The one or more NTCRM of claim 10 , wherein the instructions, when executed, are further to cause the circuitry to store a history of prior indications of the one or more current utilization measurements for the first core exceeding the threshold, wherein the determination to throttle is based further on the history of prior indications.
12. The one or more NTCRM of claim 11 , wherein the instructions, when executed, are further to cause the circuitry to increment or decrement a counter based on the indications during a measurement window, wherein the determination to throttle is based on a value of the counter.
13. The one or more NTCRM of claim 10 , wherein the one or more current utilization measurements for the first core correspond to respective active periods of the first core.
14. The one or more NTCRM of claim 10 , wherein the instructions, when executed, are further to cause the circuitry to:
determine that a percentage of time that the first core is throttled has exceeded a throttling threshold, wherein the determining whether to change the allocation of the power budget for the first core is based on the percentage of time that the first core is throttled exceeding the throttling threshold.
15. The one or more NTCRM of claim 10 , wherein the threshold is different for two or more of the plurality of processor cores.
16. The one or more NTCRM of claim 10 , wherein the instructions, when executed, are to cause the circuitry to change the allocation of the power budget for the first core by lowering a frequency of the first core.
17. The one or more NTCRM of claim 10 , wherein the instructions, when executed, are to cause the circuitry to change the allocation of the power budget for the first core by increasing the threshold.
18. A computing system comprising:
a motherboard;
a multicore processor coupled to the motherboard, the multicore processor including:
a plurality of processor cores;
a plurality of current sensors to provide indications of whether one or more current utilization measurements of respective ones of the plurality of processor cores exceeds a threshold; and
control circuitry to:
determine to throttle a first processor core of the plurality of processor cores based on the indications; and
send a throttle request to the first processor core based on the determination, the first processor core to throttle according to a default throttling parameter if the throttle request does not indicate a throttling parameter.
19. The computing system of claim 18 , further comprising a voltage regulator coupled to the multicore processor, the voltage regulator to provide a supply voltage to the multicore processor, wherein the voltage regulator is to enter an overcurrent state based on an overcurrent threshold.
20. The computing system of claim 18 , wherein the indications include a present indication and historical indications for the first processor core.
21. The computing system of claim 18 , wherein the first processor core is to throttle according to a default degree of throttling if the throttle request does not indicate a degree of throttling.
22. The computing system of claim 18 , wherein the first processor core is to throttle according to a default throttling period if the throttle request does not indicate a throttling period.