Signal processing method and apparatus

1. A signal processing method comprising:

receiving a signal matrix and a weight matrix;

partitioning the signal matrix to obtain X×H fractal signal matrices;

partitioning the weight matrix to obtain H×Y fractal weight matrices, wherein the X×H fractal signal matrices and the H×Y fractal weight matrices form X×H×Y matrix multiplications;

obtaining an operation sequence of the X×H×Y matrix multiplications based on performance parameters, wherein the performance parameters comprise power consumption of reading an X×H fractal signal matrix from a first cache, power consumption of reading an H×Y fractal weight matrix from a second cache, and power consumption of reading an operation result of an X×H×Y matrix multiplication from a third cache;

processing the X×H×Y matrix multiplications based on the operation sequence to obtain X×Y result matrices by accumulating operation results of a plurality of the X×H×Y matrix multiplications; and

outputting a signal processing result that comprises the X×Y result matrices.

2. The signal processing method of claim 1 , further comprising:

selecting a first matrix multiplication from the X×H×Y matrix multiplications; and

sequentially searching for a second matrix multiplication to an (X×H×Y) th matrix multiplication using the first matrix multiplication as a start point, to obtain the operation sequence,

wherein searching a k th matrix multiplication comprises selecting a matrix multiplication with a smallest cost value as the k th matrix multiplication based on a cost value of transiting from a (k−1) th matrix multiplication to one of the X×H×Y matrix multiplications, wherein k is an integer greater than or equal to 2 and less than or equal to X×H×Y, and wherein the k th matrix multiplication is in the X×H×Y matrix multiplications other than the first matrix multiplication to the (k−1) th matrix multiplication.

3. The signal processing method of claim 2 , further comprising determining a cost value of transiting from the (k−1) th matrix multiplication to an i th matrix multiplication using a first formula, wherein the i th matrix multiplication is an X×H×Y matrix multiplication, wherein the first formula comprises:

Zi=E ai +E bi +2 E ci ,

wherein Zi is the cost value of transiting from the (k−1) th matrix multiplication to the i th matrix multiplication, wherein E ai indicates power consumption of reading a fractal signal matrix of the i th matrix multiplication, wherein E bi indicates power consumption of reading a fractal weight matrix of the i th matrix multiplication, and wherein E ci indicates power consumption of reading an operation result of the i th matrix multiplication.

4. The signal processing method of claim 3 , wherein E ai =0 when the i th matrix multiplication reuses a fractal signal matrix in the (k−1) th matrix multiplication, wherein E ai =x1 when the i th matrix multiplication does not reuse a fractal signal matrix of the (k−1) th matrix multiplication, and wherein x1 is greater than zero.

5. The signal processing method of claim 3 , wherein E bi =0 when the i th matrix multiplication reuses a fractal weight matrix of the (k−1) th matrix multiplication, wherein E bi =x2 when the i th matrix multiplication does not reuse a fractal weight matrix of the (k−1) th matrix multiplication, and wherein x2 is greater than zero.

6. The signal processing method of claim 3 , wherein E ci =0 when the i th matrix multiplication reuses a fractal result matrix of the (k−1) th matrix multiplication, wherein E ci =x3 when the i th matrix multiplication does not reuse an operation result of the (k−1) th matrix multiplication, and wherein x3 is greater than zero.

7. The signal processing method of claim 2 , wherein the performance parameters further comprise bandwidth parameters that are based on a read/write bandwidth of the first cache, a read/write bandwidth of the second cache, and a read/write bandwidth of the third cache, and wherein the bandwidth parameters comprise a bandwidth penalty value of reading the one of the X×H fractal signal matrices from the first cache, a bandwidth penalty value of reading the one of the H×Y fractal weight matrices from the second cache, and a bandwidth penalty value of reading the operation result of the X×H×Y matrix multiplication from the third cache.

8. The signal processing method of claim 7 , further comprising determining a cost value of transiting from the (k−1) th matrix multiplication to an i th matrix multiplication using a second formula, wherein the i th matrix multiplication is one of the X×H×Y matrix multiplications, wherein the second formula comprises:

Zi =( E ai +P ai )+( E bi +P bi )+(2 E ci +2 P ci ),

wherein Zi is the cost value of transiting from the (k−1) th matrix multiplication to the i th matrix multiplication, wherein E ai indicates power consumption of reading a fractal signal matrix of the i th matrix multiplication from the first cache, wherein E bi indicates power consumption of reading a fractal weight matrix of the i th matrix multiplication from the second cache, wherein E ci indicates power consumption of reading an operation result of the i th matrix multiplication from the third cache, wherein P ai indicates a bandwidth penalty value of reading the fractal signal matrix of the i th matrix multiplication from the first cache, wherein P bi indicates a bandwidth penalty value of reading the fractal weight matrix of the i th matrix multiplication from the second cache, and wherein P ci indicates a bandwidth penalty value of reading the operation result of the i th matrix multiplication from the third cache.

9. The signal processing method of claim 8 , wherein E ai =0 and P ai =0 when the i th matrix multiplication reuses a fractal signal matrix of the (k−1) th matrix multiplication, wherein E ai =x1 and P ai =y1 when the i th matrix multiplication does not reuse a fractal signal matrix of the (k−1) th matrix multiplication, and wherein x1 and y1 are greater than zero.

10. The signal processing method of claim 8 , wherein E bi =0 and P bi =0 when the i th matrix multiplication reuses a fractal weight matrix of the (k−1) th matrix multiplication, wherein E bi =x2 and P bi =y2 when the i th matrix multiplication does not reuse a fractal weight matrix of the (k−1) th matrix multiplication, and wherein x2 and y2 are greater than zero.

11. The signal processing method of claim 8 , wherein E ci =0 and P ci =0 when the i th matrix multiplication reuses an operation result of the (k−1) th matrix multiplication, wherein E ci =x3 and P ci =y3 when the i th matrix multiplication does not reuse an operation result of the (k−1) th matrix multiplication, and wherein x3 and y3 are greater than zero.

12. A signal processing apparatus comprising:

an input interface configured to receive a signal matrix and a weight matrix;

a processor coupled to the input interface and configured to:

partition the signal matrix to obtain X×H fractal signal matrices;

partition the weight matrix to obtain H×Y fractal weight matrices, wherein the X×H fractal signal matrices and the H×Y fractal weight matrices form X×H×Y matrix multiplications;

obtain an operation sequence of the X×H×Y matrix multiplications based on performance parameters, wherein the performance parameters comprise power consumption of reading an X×H fractal signal matrix from a first cache, power consumption of reading an H×Y fractal weight matrix from a second cache, and power consumption of reading an operation result of an X×H×Y matrix multiplications from a third cache; and

process the X×H×Y matrix multiplications based on the operation sequence to obtain X×Y result matrices by accumulating operation results of a plurality of the X×H×Y matrix multiplications; and

an output interface coupled to the processor and configured to output a signal processing result that comprises the X×Y result matrices.

13. The signal processing apparatus of claim 12 , wherein the processor is further configured to:

select a first matrix multiplication from the X×H×Y matrix multiplications; and

sequentially search for a second matrix multiplication to an (X×H×Y) th matrix multiplication using the first matrix multiplication as a start point to obtain the operation sequence,

wherein searching a k th matrix multiplication comprises selecting a matrix multiplication with a smallest cost value as the k th matrix multiplication based on a cost value of transiting from a (k−1) th matrix multiplication to one of the X×H×Y matrix multiplications, wherein k is an integer greater than or equal to 2 and less than or equal to X×H×Y, and wherein the k th matrix multiplication is in the X×H×Y matrix multiplications other than the first matrix multiplication to the (k−1) th matrix multiplication.

14. The signal processing apparatus of claim 13 , wherein the processor is further configured to determine a cost value of transiting from the (k−1) th matrix multiplication to an i th matrix multiplication using a first formula, wherein the i th matrix multiplication is an X×H×Y matrix multiplication, and wherein the first formula comprises:

Zi=E ai +E bi +2 E ci ,

wherein Zi is the cost value of transiting from the (k−1) th matrix multiplication to the i th matrix multiplication, wherein E ai indicates power consumption of reading a fractal signal matrix of the i th matrix multiplication, wherein E bi indicates power consumption of reading a fractal weight matrix of the i th matrix multiplication, and wherein E ci indicates power consumption of reading an operation result of the i th matrix multiplication.

15. The signal processing apparatus of claim 14 , wherein E ai =0 when the i th matrix multiplication reuses a fractal signal matrix of the (k−1) th matrix multiplication, wherein E ai =x1 when the i th matrix multiplication does not reuse a fractal signal matrix of the (k−1) th matrix multiplication, and wherein x1 is greater than zero.

16. The signal processing apparatus of claim 14 , wherein E bi =0 when the i th matrix multiplication reuses a fractal weight matrix of the (k−1) th matrix multiplication, wherein E bi =x2 when the i th matrix multiplication does not reuse a fractal weight matrix of the (k−1) th matrix multiplication, and wherein x2 is greater than zero.

17. The signal processing apparatus of claim 14 , wherein E ci =0 when the i th matrix multiplication reuses an operation result of the (k−1) th matrix multiplication, wherein E ci =x3 when the i th matrix multiplication does not reuse a result matrix of the (k−1) th matrix multiplication, and wherein x3 is greater than zero.

18. The signal processing apparatus of claim 13 , wherein the performance parameters further comprise bandwidth parameters that are based on read/write bandwidth of the first cache, read/write bandwidth of the second cache, and read/write bandwidth of the third cache, and wherein the bandwidth parameters comprise a bandwidth penalty value of reading the one of the X×H fractal signal matrices from the first cache, a bandwidth penalty value of reading the one of the H×Y fractal weight matrices from the second cache, and a bandwidth penalty value of reading the operation result of the X×H×Y matrix multiplication from the third cache.

19. The signal processing apparatus according to claim 18 , wherein the processor determines, in the following manner, a cost value of transiting from the (k−1) th matrix multiplication to an i th matrix multiplication, wherein the i th matrix multiplication is one of the X×H×Y matrix multiplications:

Zi =( E ai +P ai )+( E bi +P bi )+(2 E ci +2 P ci ),

wherein Zi is the cost value of transiting from the (k−1) th matrix multiplication to the i th matrix multiplication, wherein E ai indicates power consumption of reading a fractal signal matrix of the i th matrix multiplication from the first cache, wherein E bi indicates power consumption of reading a fractal weight matrix of the i th matrix multiplication from the second cache, wherein E ci indicates power consumption of reading an operation result of the i th matrix multiplication from the third cache, wherein P ai indicates a bandwidth penalty value of reading the fractal signal matrix of the i th matrix multiplication from the first cache, wherein P bi indicates a bandwidth penalty value of reading the fractal weight matrix of the i th matrix multiplication from the second cache, and wherein P ci indicates a bandwidth penalty value of reading the operation result of the i th matrix multiplication from the third cache.

20. The signal processing apparatus of claim 19 , wherein:

E ai =0 and P ai =0 when the i th matrix multiplication reuses a fractal signal matrix of the (k−1) th matrix multiplication, and E ai =x1 and P ai =y1 when i th matrix multiplication does not reuse a fractal signal matrix of the (k−1) th matrix multiplication;

E bi =0 and P bi =0 when the i th matrix multiplication reuses a fractal weight matrix of the (k−1) th matrix multiplication, and E bi =x2 and P bi =y2 when the i th matrix multiplication does not reuse a fractal weight matrix of the (k−1) th matrix multiplication; or

E ci =0 and P ci =0 when the i th matrix multiplication reuses an operation result of the (k−1) th matrix multiplication, and E ci =x3 and P ci =y3 when the i th matrix multiplication does not reuse an operation result of the (k−1) th matrix multiplication,

wherein x1, x2, x3, y1, y2, and y3 are all greater than zero.