IP Library › Granted Patent US 11,238,771
Granted Patent B2
US 11,238,771 · App. 16/772,476 · Granted Feb 1, 2022

Display driver circuit for synchronizing output timing of images in low power state

Inventors: Jongkon Bae (Gyeonggi-do, KR); Yohan Lee (Gyeonggi-do, KR); Yunpyo Hong (Gyeonggi-do, KR); Dongkyoon Han (Gyeonggi-do, KR)
G09G3/20G06F1/3265G06F3/147G09G5/10G09G2310/08G09G2320/062
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,238,771
App. No.
16/772,476
Granted
Feb 1, 2022
Kind
B2
Abstract

An electronic device according to an embodiment of the present invention comprises: a housing; a display panel disposed inside the housing; a display driver circuit electrically connected to the display panel; and a processor for generating a background image output through the display panel to transmit the same to the display driver circuit.

Claims (41)

1. An electronic device comprising:

a housing,

a display panel arranged in the housing,

a display driving circuit electrically connected to the display panel, and

a processor configured to generate a background image output through the display panel and transmit the background image to the display driving circuit,

wherein the display driving circuit is configured to:

determine whether a first object is displayed in a first area of the background image that is not exposed to an outside by the housing when the background image is received,

generate a partial image having a size smaller than a size of the background image when the first object is not displayed as the determination result, and

merge the partial image and a second area of the background image that is exposed to the outside and output a merging result through the display panel.

2. The electronic device of claim 1 , wherein the display driving circuit is configured to extract a color value of the first object and adjust brightness of the partial image based on the extracted color value.

3. The electronic device of claim 1 , wherein the display driving circuit is configured to:

generate an additional object in the first area when receiving the background image, and

merge the partial image and the second area and output a merging result through the display panel.

4. The electronic device of claim 1 , wherein the processor is configured to generate the partial image, and

wherein the display driving circuit includes a memory configured to store the partial image generated from the processor.

5. The electronic device of claim 4 , wherein the display driving circuit is configured to merge the partial image stored in the memory and the second area and output a merging result through the display panel.

6. The electronic device of claim 1 , wherein the processor is configured to transmit a background image that does not include the first object to the display driving circuit.

7. The electronic device of claim 1 , wherein the display driving circuit is configured to:

determine whether a second object is displayed in the second area, and

merge the partial image and the second area to output a merging result through the display panel when the second object is not displayed as the determination result.

8. The electronic device of claim 7 , wherein the controller is configured to extract a color value of the second object and adjust brightness of the partial image based on the extracted color value.

9. The electronic device of claim 7 , wherein the processor is configured to remove the second object from the second area and transmit a removing result to the display driving circuit.

10. A display driving circuit comprising:

a receiving circuit configured to sequentially receive a first background image and a second background image from an external processor,

an up-scaler electrically connected to the receiving circuit and extract a first tracking point and a second tracking point generated in some areas of the first background image and the second background image, and

a controller electrically connected to the up-scaler,

wherein the controller is configured to:

generate a first partial image when the first background image is received from the receiving circuit,

output the first partial image at a position corresponding to a coordinate value of the first tracking point on the first background image,

generate a second partial image when the second background image is received from the receiving circuit,

calculate a difference between the coordinate values of the first tracking point and the second tracking point,

move the second partial image from the coordinate value of the first tracking point by a distance corresponding to the difference between the coordinate values of the first tracking point and the second tracking point and output the second partial image onto the second background image.

11. The display driving circuit of claim 10 , wherein the controller is configured to:

calculate a difference between color values of the first tracking point and the second tracking point, and

adjust brightness of the second partial image based on the difference between the color values.

12. The display driving circuit of claim 10 , wherein the second tracking point is first recognized by the controller than the second partial image.

13. The display driving circuit of claim 10 , wherein the first tracking point includes plural pieces of pixel information, and

wherein the controller is configured to output the first partial image to a position corresponding to a coordinate value of a specified pixel among the plural pieces of pixel information.

14. The display driving circuit of claim 13 , wherein the controller is configured to adjust brightness of the first partial image based on a color value of the specified pixel.

15. The display driving circuit of claim 10 , wherein the first partial image and the second partial image are generated from the external processor, and

wherein the receiving circuit is configured to receive the first partial image and the second partial image from the external processor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2020
From: BAE, JONGKON; LEE, YOHAN; HONG, YUNPYO; HAN, DONGKYOON
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 053009/0516 →
Priority Claims (1)
KR 10-2017-0176085 · Dec 20, 2017 · national
Continuity (1)
Related Publication 20200388202A1 · Dec 10, 2020
Cited By (1)
US 12,626,634