IP Library › Granted Patent US 11,239,159
Granted Patent B2
US 11,239,159 · App. 15/931,816 · Granted Feb 1, 2022

Semiconductor device

Inventors: Yasuhiro Murase (Nagaokakyo, JP); Tomoyuki Ashimine (Nagaokakyo, JP); Hiroshi Nakagawa (Nagaokakyo, JP)
Assignee: MURATA MANUFACTURING CO., LTD.
H01L23/5228H01L23/5222H01L23/5227H01L27/0203H01L28/10H01L28/20H01L28/40
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Quick Facts
Patent No.
US 11,239,159
App. No.
15/931,816
Granted
Feb 1, 2022
Kind
B2
Abstract

A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface, a first electrode opposing the first main surface of the semiconductor substrate, a dielectric layer between the semiconductor substrate and the first electrode, a first resistance control layer on the first electrode, a wiring part on the first resistance control layer, and a second electrode opposing the second main surface of the semiconductor substrate. The first resistance control layer includes a first region that has a first electrical resistivity and that electrically connects the first electrode and the wiring part, and a second region that is aligned with the first region and has a second electrical resistivity higher than the first electrical resistivity of the first region.

Claims (35)

1. A semiconductor device comprising:

a semiconductor substrate that has a first main surface and a second main surface;

a first electrode opposing the first main surface of the semiconductor substrate;

a dielectric layer between the semiconductor substrate and the first electrode;

a first resistance control layer on the first electrode;

a wiring part on the first resistance control layer; and

a second electrode opposing the second main surface of the semiconductor substrate,

wherein the first resistance control layer includes a first region that has a first electrical resistivity and that electrically connects the first electrode and the wiring part, and a second region that is aligned with the first region and has a second electrical resistivity higher than the first electrical resistivity of the first region.

2. The semiconductor device according to claim 1 , wherein the first electrical resistivity of the first region is equal to or higher than a third electrical resistivity of the wiring part.

3. The semiconductor device according to claim 1 , wherein the first electrical resistivity of the first region is equal to or higher than a third electrical resistivity of the first electrode.

4. The semiconductor device according to claim 1 , wherein a third electrical resistivity of the wiring part is equal to or higher than a fourth electrical resistivity of the first electrode.

5. The semiconductor device according to claim 1 , wherein, in a cross-sectional view perpendicular to the first main surface of the semiconductor substrate through a central portion of the first region of the first resistance control layer, a width of the first region in a direction parallel to the first main surface is larger than a thickness of the first region in a direction perpendicular to the first main surface.

6. The semiconductor device according to claim 1 , wherein the second region of the first resistance control layer is an insulator.

7. The semiconductor device according to claim 6 , wherein

the first electrode comprises silicon, and

the second region of the first resistance control layer comprises a silicon oxide.

8. The semiconductor device according to claim 1 , wherein the first region and the second region of the first resistance control layer comprise a semiconductor.

9. The semiconductor device according to claim 1 , wherein the semiconductor substrate comprises silicon.

10. The semiconductor device according to claim 9 , wherein a third electrical resistivity of the semiconductor substrate is 10 −4 Ω·cm to 10 −2 Ω·cm.

11. The semiconductor device according to claim 1 , further comprising:

a trench structure including at least one trench portion extending into the semiconductor substrate from the first main surface of the semiconductor substrate, wherein

the dielectric layer and the first electrode extend along the trench structure.

12. The semiconductor device according to claim 11 , wherein the first region of the first resistance control layer is outside the at least one trench portion of the trench structure when viewed in a plan view of the semiconductor device.

13. The semiconductor device according to claim 1 , further comprising:

a second resistance control layer between the semiconductor substrate and the second electrode,

wherein the second resistance control layer includes a third region that has a third electrical resistivity and that electrically connects the semiconductor substrate and the second electrode, and a fourth region that is aligned with the third region and has a fourth electrical resistivity higher than the third electrical resistivity of the third region.

14. The semiconductor device according to claim 13 , wherein the third electrical resistivity of the third region of the second resistance control layer is equal to or higher than a fifth electrical resistivity of the second electrode.

15. The semiconductor device according to claim 13 , wherein the third electrical resistivity of the third region of the second resistance control layer is equal to or higher than a fifth electrical resistivity of the semiconductor substrate.

16. The semiconductor device according to claim 13 , wherein a fifth electrical resistivity of the semiconductor substrate is equal to or higher than a sixth electrical resistivity of the second electrode.

17. The semiconductor device according to claim 13 , wherein, in a cross-sectional view perpendicular to the second main surface of the semiconductor substrate through a central portion of the third region of the second resistance control layer, a width of the third region in a direction parallel to the second main surface is larger than a thickness of the third region in a direction perpendicular to the second main surface.

18. The semiconductor device according to claim 13 , wherein the fourth region of the second resistance control layer is an insulator.

19. The semiconductor device according to claim 18 , wherein the fourth region of the second resistance control layer comprises a silicon oxide.

20. The semiconductor device according to claim 13 , wherein the third region and the fourth region of the second resistance control layer comprise a semiconductor.

21. The semiconductor device according to claim 1 , wherein the wiring part is patterned as an inductor.

22. A circuit comprising the semiconductor device according to claim 1 connected in parallel between a drain and a source or between a collector and an emitter of a transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2020
From: MURASE, YASUHIRO; ASHIMINE, TOMOYUKI; NAKAGAWA, HIROSHI
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 052661/0218 →
Priority Claims (1)
JP JP2017-254518 · Dec 28, 2017 · national
Continuity (2)
Continuation PCTJP2018047719 · Dec 26, 2018
Related Publication 20200273796A1 · Aug 27, 2020