Passive device module and semiconductor package including the same

1. A semiconductor package, comprising:

a lower redistribution layer including wiring patterns;

a lower substrate on the lower redistribution layer, the lower substrate including a cavity;

an application processor on the lower redistribution layer in the cavity;

a cache memory chip on the application processor;

a passive device module on the application processor;

a plurality of first through-silicon vias penetrating the application processor to connect the lower redistribution layer to the passive device module; and

lower bumps on a bottom surface of the lower redistribution layer,

wherein:

the passive device module is adjacent to a side of the cache memory chip,

the passive device module includes:

a module substrate;

at least one inductor on the module substrate; and

a plurality of capacitors,

the plurality of capacitors includes first capacitors disposed side-by-side in a first direction, and

the at least one inductor surrounds the first capacitors.

2. The semiconductor package as claimed in claim 1 , wherein the plurality of capacitors further includes second capacitors disposed side-by-side in a second direction perpendicular to the first direction.

3. The semiconductor package as claimed in claim 2 , wherein the at least one inductor surrounds the second capacitors in a top view.

4. The semiconductor package as claimed in claim 2 , wherein the at least one inductor is at an intersection between the first capacitors disposed side-by-side in the first direction and the second capacitors disposed side-by-side in the second direction.

5. The semiconductor package as claimed in claim 1 , further comprising a plurality of second through-silicon vias penetrating the application processor to connect the cache memory chip to the application processor.

6. The semiconductor package as claimed in claim 5 , further comprising a lower encapsulation layer, wherein the lower encapsulation layer:

is between the cache memory chip and the passive device module in the cavity, and

covers side surfaces of the passive device module, the cache memory chip, and the application processor.

7. The semiconductor package as claimed in claim 6 , wherein a top surface of the lower encapsulation layer and top surfaces of the lower substrate and the cache memory chip are coplanar.

8. The semiconductor package as claimed in claim 1 , further comprising:

an upper redistribution layer on the passive device module; and

a plurality of via connectors in the lower substrate,

wherein the via connectors electrically connect the upper redistribution layer to the lower redistribution layer.

9. A semiconductor package, comprising:

a lower redistribution layer including a plurality of wiring patterns;

a lower substrate on the lower redistribution layer, the lower substrate including a cavity;

an application processor on the lower redistribution layer in the cavity;

a cache memory chip on the application processor;

a first passive device module on a top surface of the application processor and adjacent to a first edge of the application processor;

a plurality of first through-silicon vias penetrating the application processor and electrically connecting the application processor to the first passive device module;

a plurality of second through-silicon vias penetrating the application processor and electrically connecting the application processor to the cache memory chip; and

lower bumps on a bottom surface of the lower redistribution layer,

wherein:

the first passive device module is adjacent to a first side of the cache memory chip,

the first passive device module includes:

a first module substrate;

at least one first inductor on the first module substrate; and

a plurality of first capacitors, and

the at least one first inductor surrounds the plurality of first capacitors.

10. The semiconductor package as claimed in claim 9 , wherein the plurality of first capacitors is disposed parallel to the first side of the cache memory chip in a top view.

11. The semiconductor package as claimed in claim 9 , further comprising a second passive device module on the top surface of the application processor and adjacent to a second edge of the application processor.

12. The semiconductor package as claimed in claim 11 , wherein:

the second passive device module includes:

a second module substrate;

at least one second inductor on the second module substrate; and

a plurality of second capacitors, and

the at least one second inductor surrounds the plurality of second capacitors in a top view.

13. A semiconductor package, comprising:

a lower package;

an upper package stacked on the lower package; and

a plurality of upper bumps configured to connect the lower package to the upper package,

wherein the lower package includes:

a lower redistribution layer including a plurality of wiring patterns;

a lower substrate including a cavity;

an application processor on the lower redistribution layer in the cavity;

a cache memory chip on the application processor;

a passive device module in a first region of a top surface of the application processor; and

lower bumps on a bottom surface of the lower redistribution layer, and

wherein:

the passive device module is adjacent and parallel to at least one side surface of the cache memory chip,

the passive device module includes:

a module substrate;

at least one inductor on the module substrate; and

a plurality of capacitors, and

the at least one inductor surrounds the plurality of capacitors.

14. The semiconductor package as claimed in claim 6 , wherein:

the passive device module is adjacent to at least two side surfaces of the cache memory chip, and

the plurality of capacitors is disposed parallel to the at least two side surfaces of the cache memory chip.

15. The semiconductor package as claimed in claim 1 , wherein the at least one inductor continuously extends in the first direction along sides of the first capacitors.

16. The semiconductor package as claimed in claim 9 , wherein the at least one first inductor continuously extends along sides of the plurality of first capacitors.

17. The semiconductor package as claimed in claim 13 , wherein the at least one inductor continuously extends along sides of the plurality of capacitors.