Partial buried insulator nano-sheet device
View Patent ↗Devices and methods are described herein that obviate the need for a read assist circuit. In one example, a semiconductor device includes a source region and a drain region formed above a substrate. A buried insulator (BI) layer is formed beneath either the source region or the drain region. A first nano-sheet is formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer. The BI layer reduces current flow through the first nano-sheet.
1. A semiconductor device comprising:
a source region and a drain region formed above a substrate;
a buried insulator (BI) layer formed beneath only one of the source region or the drain region and above the substrate; and
a first nano-sheet formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer.
2. The semiconductor device of claim 1 further comprising:
a gate formed surrounding the first nano-sheet;
an insulator layer formed vertically above the first nano-sheet, the insulator layer separating the first nano-sheet from a second nano-sheet; and
the second nano-sheet formed above the insulator layer, wherein the gate is formed above the second nano-sheet.
3. The semiconductor device of claim 1 , wherein the semiconductor device is not coupled to a read assist circuit.
4. The semiconductor device of claim 2 , wherein the first nano-sheet and the second nano-sheet each comprise a semiconductor material having at least one of Si, P, Ge, Ga, SiGe, or InAS.
5. The semiconductor device of claim 1 , wherein the BI layer comprises a dielectric material having at least one of Si 3 N 4 , SiO 2 , Al 2 O 3 , HfO 2 , Ta 2 O 5 , or TiO 2 .
6. The semiconductor device of claim 1 , wherein a depth of the BI layer is between approximately (i) 30 times a length of a gate and (ii) 0.5 times a depth of the gate.
7. The semiconductor device of claim 1 , wherein a width of the BI layer is greater than or equal to a width of the first nano-sheet.
8. The semiconductor device of claim 7 , wherein the width of the first nano-sheet is between approximately (i) 10 times a length of a gate and (ii) 0.5 times the length of the gate.
9. The semiconductor device of claim 1 , wherein a length of the BI layer is greater than or equal to a spacing between a gate and a gate of another semiconductor device.
10. A static random access memory (SRAM) device comprising:
a plurality of SRAM bitcells, each SRAM bitcell comprising:
a portion of a buried insulator (BI) layer formed beneath only a first source/drain region;
a plurality of nano-sheet layers separating the first source/drain region from a second source/drain region; and
a bitline coupling together the plurality of the SRAM bitcells, the bitline electrically coupled to the portion of the BI layer.
11. The SRAM device of claim 10 , wherein no bitcell of the plurality of bitcells is coupled to a read assist circuit.
12. The SRAM device of claim 10 , wherein the plurality of nano-sheets each comprise a semiconductor material having at least one of Si, P, Ge, Ga, SiGe, or InAS.
13. The SRAM device of claim 10 , wherein the BI layer comprises a dielectric material having at least one of Si 3 N 4 , SiO 2 , Al 2 O 3 , HfO 2 , Ta 2 O 5 , or TiO 2 .
14. The SRAM device of claim 10 , wherein the plurality of nano-sheets are separated from each other via a plurality of insulating layers.
15. The SRAM device of claim 10 , wherein the plurality of nano-sheets are vertically positioned above the portion of the BI layer.
16. The SRAM device of claim 10 , wherein each of the SRAM bitcells comprise a first transistor coupled to a second transistor and a first current through the first transistor, wherein the first current is less than a second current through the second transistor.
17. A method comprising:
forming a first nano-sheet above a substrate;
depositing a first gate electrode layer above the first nano-sheet;
forming a buried insulator (BI) layer above the substrate; and
forming only one of a source region or a drain region above the BI layer, wherein the first nano-sheet is positioned (i) horizontally between the source region or the drain region and (ii) vertically above the BI layer.
18. The method of claim 17 further comprising:
forming a gate above the first nano-sheet;
forming an insulator layer vertically above the first nano-sheet, the insulator layer separating the first nano-sheet from a second nano-sheet; and
forming the second nano-sheet above the insulator layer, wherein the gate is formed above the second nano-sheet.
19. The method of claim 18 , wherein the first nano-sheet and the second nano-sheet each are formed using a semiconductor material having at least one of Si, P, Ge, Ga, SiGe, or InAS.
20. The method of claim 16 , wherein the BI layer is formed using a dielectric material having at least one of Si 3 N 4 , SiO 2 , Al 2 O 3 , HfO 2 , Ta 2 O 5 , or TiO 2 .