Isolation features and methods of fabricating the same
Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.
1. A semiconductor device, comprising:
a first fin structure and a second fin structure each extending from a substrate;
a first gate segment over the first fin structure and a second gate segment over the second fin structure, the first and second gate segments aligned along a lengthwise direction;
a first isolation feature that separates the first and second gate segments;
a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment;
a second S/D feature over the second fin structure and adjacent to the second gate segment; and
a second isolation feature disposed between the first and second S/D features,
wherein a composition of the second isolation feature is different from a composition of the first isolation feature,
wherein a top width of the first isolation feature along the lengthwise direction is greater than a bottom width of the first isolation feature along the lengthwise direction such that the first isolation feature comprises first tapered sidewalls,
wherein a top width of the second isolation feature along the lengthwise direction is greater than a bottom width of the second isolation feature along the lengthwise direction such that the second isolation feature comprises second tapered sidewalls,
wherein the first tapered sidewalls are aligned with the second tapered sidewalls along a direction perpendicular to the lengthwise direction.
2. The semiconductor device of claim 1 , wherein each of the first fin structure and the second fin structure comprises at least one fin.
3. The semiconductor device of claim 1 , wherein the second isolation feature is free of silicon nitride.
4. The semiconductor device of claim 1 , wherein the second isolation feature comprises a sheet-like void.
5. The semiconductor device of claim 1 , wherein the first isolation feature comprises silicon oxide over silicon nitride.
6. The semiconductor device of claim 1 , wherein the first isolation feature comprises silicon nitride.
7. The semiconductor device of claim 6 ,
wherein the first and second gate segments each comprises a dielectric layer and a conductive layer,
wherein the dielectric layer is not in contact with silicon nitride of the first isolation feature, and
wherein the conductive layer is in contact with silicon nitride of the first isolation feature.
8. A semiconductor device, comprising:
a first fin structure and a second fin structure each extending from a substrate;
a first gate segment over the first fin structure;
a second gate segment over the second fin structure;
a first isolation feature between and in contact with the first gate segment and the second gate segment, the first isolation feature comprising a silicon oxide layer lined by a silicon nitride layer;
a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment;
a second S/D feature over the second fin structure and adjacent to the second gate segment; and
a source/drain (S/D) contact disposed over the first S/D feature and the second S/D feature,
wherein a portion of the S/D contact extends between the first S/D feature and the second S/D feature,
wherein the first and second gate segments each comprises a dielectric layer and a conductive layer,
wherein the dielectric layer is not in contact with silicon nitride layer of the first isolation feature, and
wherein the conductive layer is in contact with silicon nitride of the first isolation feature.
9. The semiconductor device of claim 8 , wherein the first isolation feature comprises silicon nitride.
10. The semiconductor device of claim 8 ,
wherein the silicon oxide layer is spaced apart from the conductive layer of the first gate segment and the second gate segment,
wherein the silicon oxide layer is in direct contact with the dielectric layer of the first gate segment and the second gate segment.
11. The semiconductor device of claim 8 , wherein the first isolation feature consists essentially of silicon nitride.
12. The semiconductor device of claim 8 , further comprising:
a second isolation feature disposed between the first S/D feature and the second S/D feature,
wherein the second isolation feature is disposed below the S/D contact.
13. The semiconductor device of claim 12 , wherein the second isolation feature comprises silicon oxide.
14. The semiconductor device of claim 12 , wherein the second isolation feature consists essentially of silicon oxide.
15. A semiconductor device, comprising:
a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure each extending from a substrate;
a first gate segment over the first fin structure and second fin structure;
a second gate segment over the third fin structure and the fourth fin structure;
a first isolation feature between the first gate segment and the second gate segment, the first isolation feature comprising an oxygen-containing dielectric layer and an oxygen-free dielectric layer;
a first source/drain (S/D) feature over the first fin structure and the second fin structure;
a second S/D feature over the third fin structure and the fourth fin structure; and
a source/drain (S/D) contact disposed over the first S/D feature and the second S/D feature,
wherein a portion of the S/D contact extends between the first S/D feature and the second S/D feature,
wherein the first and second gate segments each comprises a dielectric layer and a conductive layer,
wherein the dielectric layer of the first and second gate segments is in direct contact with the oxygen-containing dielectric layer and the conductive layer of the first and second gate segments is in direct contact with the oxygen-free dielectric layer.
16. The semiconductor device of claim 15 , wherein the portion of the S/D contact comprises a depth between about 20 nm and 40 nm.
17. The semiconductor device of claim 15 ,
wherein the portion of the S/D contact comprises a width between the first S/D feature and the second S/D feature,
wherein the width is between about 20 nm and 30 nm.
18. The semiconductor device of claim 15 ,
wherein the first S/D feature extends continuously from the first fin structure to the second fin structure,
wherein the second S/D feature extends continuously from the third fin structure to the fourth fin structure.
19. The semiconductor device of claim 15 , further comprising:
a shallow trench isolation layer disposed between the second fin structure and the third fin structure.
20. The semiconductor device of claim 19 , further comprising:
a second isolation feature disposed between the first S/D feature and the second S/D feature,
wherein the second isolation feature is disposed below the S/D contact and within the shallow trench isolation layer,
wherein a composition of the second isolation feature is different from a composition of the shallow trench isolation layer.