Caching device, cache, system, method and apparatus for processing data, and medium

1. A caching device, comprising a first queue, a second queue, a write port group, a read port, a first pop-up port, a second pop-up port and a press-in port, wherein

the write port group is configured to write cache data into a set storage address in the first queue and/or the second queue;

the read port is configured to read all cache data from the first queue and/or the second queue at one time;

the press-in port is configured to press cache data into the first queue and/or the second queue;

the first pop-up port is configured to pop up cache data from the first queue; and

the second pop-up port is configured to pop up cache data from the second queue.

2. The caching device according to claim 1 , wherein the write port group comprises a write data port and a write address port,

the write data port is configured to receive written cache data; and

the write address port is configured to receive a storage address in the first queue and/or the second queue, the cache data written by the write data port being to be written to the address.

3. The caching device according to claim 2 , wherein the write port group further comprises a write mask port,

the write mask port is configured to receive mask information of the cache data written by the write data port; and

the mask information is configured to indicate a data bit of the cache data written to the storage address, and a bit width of the write mask port is identical to a bit width of the write data port.

4. The caching device according to claim 1 , further comprising a first empty-full state flag bit group and a second empty-full state flag bit group, wherein

the first empty-full state flag bit group is configured to indicate a storage state of cache data in the first queue, and

the second empty-full state flag bit group is configured to indicate a storage state of cache data in the second queue.

5. An instruction cache, comprising a first caching device and a second caching device according to claim 1 .

6. A system for processing an instruction, comprising the instruction cache according to claim 5 , a multi-core processor and an external instruction storage device,

wherein the instruction cache is respectively connected to the external instruction storage device and a plurality of processing cores of the multi-core processor, and the instruction cache is connected to the external instruction storage device via a bus.

7. The system according to claim 6 , wherein

the multi-core processor is configured to provide, when missing of an instruction fetch occurs, a missing instruction identifier to the instruction cache;

the external instruction storage device is used to store instructions; and

the instruction cache is configured to send the missing instruction identifier to the external instruction storage device and acquire an instruction responded and written back by the external instruction storage device via the bus.

8. The system according to claim 7 , wherein

the first caching device is configured to cache, using a first queue, an instruction fetch missing identifier that has not been responded by the external instruction storage device when the instruction fetch missing occurs, and cache, using a second queue, an missing instruction fetch identifier that has been responded but has not written back by the external instruction storage device; and

the second caching device is configured to correspondingly store, using a first queue or a second queue and based on a storage address of the missing instruction fetch identifier in the first caching device, a core identifier of a processing core matching the missing instruction fetch identifier.

9. A method for processing data, performed by an instruction cache,

wherein the instruction cache comprises a first caching device and a second caching device, both the first caching device and the second caching device have the a first queue, a second queue, a write port group, a read port, a first pop-up port, a second pop-up port and a press-in port, wherein

the write port group is configured to write cache data into a set storage address in the first queue and/or the second queue;

the read port is configured to read all cache data from the first queue and/or the second queue at one time;

the press-in port is configured to press cache data into the first queue and/or the second queue;

the first pop-up port is configured to pop up cache data from the first queue; and

the second pop-up port is configured to pop up cache data from the second queue,

wherein the method comprises:

in response to detecting that an external instruction storage device is in an idle state, fetching a missing instruction identifier from a first queue of a first caching device, and popping up the missing instruction identifier via a first pop-up port, to provide to the external instruction storage device;

in response to detecting a write-back instruction fed back by the external instruction storage device targeting at a first target missing instruction identifier, fetching the first target missing instruction identifier from a second queue of the first caching device, and popping up the first target missing instruction identifier via a second pop-up port of the first caching device;

fetching first target cache data matching the first target missing instruction identifier from a second caching device, and popping up the first target cache data through a first pop-up port or a second pop-up port of the second caching device; and

identifying, based on the first target cache data, a first target core identifier of a first target processing core matching the first target missing instruction identifier, and sending the write-back instruction to the first target processing core.

10. The method according to claim 9 , further comprising:

in response to detecting that missing of an instruction fetch targeting at a second target missing instruction identifier occurs in a second target processing core, reading all missing instruction identifiers stored in the first queue and the second queue from a read port of the first caching device;

in response to the first queue and the second queue of the first caching device not storing the second target missing instruction identifier, simultaneously storing the second target missing instruction identifier into the first queue and the second queue;

generating second target cache data based on the second target processing core and mapping relationships between preset processing cores and a corresponding data bits in cache data; and

pressing the second target cache data into a first queue or a second queue of the second caching device through a press-in port of the second caching device.

11. The method according to claim 10 , wherein after the reading all missing instruction identifiers stored in the first queue and the second queue from the read port of the first caching device, the method further comprises:

in response to the first queue or the second queue of the first caching device storing the second target missing instruction identifier, fetching a target storage address of the second target missing instruction identifier in the first caching device;

generating third target cache data and target mask information based on the second target processing core and the mapping relationships between the preset processing cores and the corresponding data bits in the cache data; and

writing the target storage address, the third target cache data and the target mask information through a write port group of the second caching device, to store, in the second caching device, a core identifier of the second target processing core matching the second target missing instruction identifier.

12. The method according to claim 9 , further comprising at least one of:

in response to there being no cache data in the first queue of the first caching device, setting an empty state flag bit in a first empty-full state flag bit group of the first caching device to a target level value;

in response to the first queue of the first caching device is full, setting a full state flag bit in the first empty-full state flag bit group of the first caching device to a target level value;

in response to there being no cache data in the second queue of the first caching device, setting an empty state flag bit in a second empty-full state flag bit group of the first caching device to a target level value; or

in response to the second queue of the first caching device is full, setting a full state flag bit in the second empty-full state flag bit group of the first caching device to a target level value.

13. The method according to claim 12 , further comprising:

in response to detecting the full state flag bit in the first empty-full state flag bit group or the second empty-full state flag bit group of the first caching device is the target level value, receiving no more instruction fetch requests from any one of processing cores in a multi-core processor.

14. A non-transitory computer readable storage medium, storing a computer instruction, wherein the computer instruction is used to cause an instruction cache to perform operations,

wherein the instruction cache comprises a first caching device and a second caching device, both the first caching device and the second caching device have the a first queue, a second queue, a write port group, a read port, a first pop-up port, a second pop-up port and a press-in port, wherein

the write port group is configured to write cache data into a set storage address in the first queue and/or the second queue;

the read port is configured to read all cache data from the first queue and/or the second queue at one time;

the press-in port is configured to press cache data into the first queue and/or the second queue;

the first pop-up port is configured to pop up cache data from the first queue; and

the second pop-up port is configured to pop up cache data from the second queue,

wherein the operations comprise:

in response to detecting that an external instruction storage device is in an idle state, fetching a missing instruction identifier from a first queue of a first caching device, and popping up the missing instruction identifier via a first pop-up port, to provide to the external instruction storage device;

in response to detecting a write-back instruction fed back by the external instruction storage device targeting at a first target missing instruction identifier, fetching the first target missing instruction identifier from a second queue of the first caching device, and popping up the first target missing instruction identifier via a second pop-up port of the first caching device;

fetching first target cache data matching the first target missing instruction identifier from a second caching device, and popping up the first target cache data through a first pop-up port or a second pop-up port of the second caching device; and

identifying, based on the first target cache data, a first target core identifier of a first target processing core matching the first target missing instruction identifier, and sending the write-back instruction to the first target processing core.

15. The medium according to claim 14 , wherein the operations further comprise:

in response to detecting that missing of an instruction fetch targeting at a second target missing instruction identifier occurs in a second target processing core, reading all missing instruction identifiers stored in the first queue and the second queue from a read port of the first caching device;

in response to the first queue and the second queue of the first caching device not storing the second target missing instruction identifier, simultaneously storing the second target missing instruction identifier into the first queue and the second queue;

generating second target cache data based on the second target processing core and mapping relationships between preset processing cores and a corresponding data bits in cache data; and

pressing the second target cache data into a first queue or a second queue of the second caching device through a press-in port of the second caching device.

16. The medium according to claim 15 , wherein after the reading all missing instruction identifiers stored in the first queue and the second queue from the read port of the first caching device, the operations further comprise:

in response to the first queue or the second queue of the first caching device storing the second target missing instruction identifier, fetching a target storage address of the second target missing instruction identifier in the first caching device;

generating third target cache data and target mask information based on the second target processing core and the mapping relationships between the preset processing cores and the corresponding data bits in the cache data; and

writing the target storage address, the third target cache data and the target mask information through a write port group of the second caching device, to store, in the second caching device, a core identifier of the second target processing core matching the second target missing instruction identifier.

17. The medium according to claim 14 , wherein the operations further comprise at least one of:

in response to there being no cache data in the first queue of the first caching device, setting an empty state flag bit in a first empty-full state flag bit group of the first caching device to a target level value;

in response to the first queue of the first caching device is full, setting a full state flag bit in the first empty-full state flag bit group of the first caching device to a target level value;

in response to there being no cache data in the second queue of the first caching device, setting an empty state flag bit in a second empty-full state flag bit group of the first caching device to a target level value; or

in response to the second queue of the first caching device is full, setting a full state flag bit in the second empty-full state flag bit group of the first caching device to a target level value.

18. The medium according to claim 17 , wherein the operations further comprise:

in response to detecting the full state flag bit in the first empty-full state flag bit group or the second empty-full state flag bit group of the first caching device is the target level value, receiving no more instruction fetch requests from any one of processing cores in a multi-core processor.