Mechanism for saving and retrieving micro-architecture context
Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block.
1. An apparatus comprising:
an execution unit within a processor to execute a code block comprising a block identifier;
power management hardware coupled to the execution unit, wherein the power management hardware is to:
monitor a first execution of the code block;
store a micro-architectural context of the processor in a metadata block, uniquely indexed in a plurality of metadata blocks by the block identifier, in response to the first execution reaching an end of the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters;
read the metadata block indexed by the block identifier upon a second execution of the code block comprising the block identifier; and
tune the second execution based on the performance data stored in the metadata block to increase efficiency of executing the code block.
2. The apparatus of claim 1 , wherein the metadata block stores the performance data collected from executing the code block on two different processor cores that have different performances, and wherein the power management hardware is to determine which one of the two different processor cores is to execute the code block based on the performance data.
3. The apparatus of claim 1 , wherein tuning the second execution based on the performance data to increase efficiency of executing the code block comprises choosing hardware resources within the execution unit to execute the code block.
4. The apparatus of claim 1 , wherein a switch code sign signifies a beginning of the metadata block.
5. The apparatus of claim 4 , wherein the switch code sign comprises at least one of a predetermined instruction and a predetermined binary code.
6. The apparatus of claim 1 , wherein the performance data is stored with a condition identifier that identifies a condition in which the performance data is collected.
7. A method performed by a processor, the method comprising:
executing a code block comprising a block identifier using an execution unit within the processor;
using power management hardware coupled to the execution unit to:
monitor a first execution of the code block;
store a micro-architectural context of the processor in a metadata block, uniquely indexed in a plurality of metadata blocks by the block identifier, in response to the first execution reaching an end of the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters;
read the metadata block indexed by the block identifier upon a second execution of the code block comprising the block identifier; and
tune the second execution based on the performance data stored in the metadata block to increase efficiency of executing the code block.
8. The method of claim 7 , wherein the metadata block stores the performance data collected from executing the code block on two different processor cores that have different performances, and wherein the power management hardware is to determine which one of the two different processor cores is to execute the code block based on the performance data.
9. The method of claim 7 , wherein tuning the second execution based on the performance data to increase efficiency of executing the code block comprises choosing hardware resources within the execution unit to execute the code block.
10. The method of claim 7 , wherein a switch code sign signifies a beginning of the metadata block.
11. The method of claim 10 , wherein the switch code sign comprises at least one of a predetermined instruction and a predetermined binary code.
12. The method of claim 7 , wherein the performance data is stored with a condition identifier that identifies a condition in which the performance data is collected.
13. A system comprising:
input and output devices;
system memory coupled to the input and output devices;
an execution unit within a processor to execute a code block comprising a block identifier;
power management hardware coupled to the execution unit, wherein the power management hardware is to:
monitor a first execution of the code block;
store a micro-architectural context of the processor in a metadata block, uniquely indexed in a plurality of metadata blocks by the block identifier, in response to the first execution reaching an end of the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters;
read the metadata block indexed by the block identifier upon a second execution of the code block comprising the block identifier; and
tune the second execution based on the performance data stored in the metadata block to increase efficiency of executing the code block.
14. The system of claim 13 , wherein the metadata block stores the performance data collected from executing the code block on two different processor cores that have different performances, and wherein the power management hardware is to determine which one of the two different processor cores is to execute the code block based on the performance data.
15. The system of claim 13 , wherein tuning the second execution based on the performance data to increase efficiency of executing the code block comprises choosing hardware resources within the execution unit to execute the code block.
16. The system of claim 13 , wherein a switch code sign signifies a beginning of the metadata block.
17. The system of claim 16 , wherein the switch code sign comprises at least one of a predetermined instruction and a predetermined binary code.
18. The system of claim 13 , wherein the performance data is stored with a condition identifier that identifies a condition in which the performance data is collected.
19. The apparatus of claim 1 , wherein the block identifier is a compiler provided block identifier.
20. The method of claim 7 , wherein the block identifier is a compiler provided block identifier.
21. The system of claim 13 , wherein the block identifier is a compiler provided block identifier.