Shift-register circuit, gate-driving circuit, and array substrate of a display panel
The present application discloses a shift-register circuit configured as one of a plurality of shift-register units cascaded in series. The shift-register circuit includes a pull-up sub-circuit coupled to a pull-up node, a first clock port, and an output port. The pull-up sub-circuit is configured to pass a first clock signal from the first clock port to the output port when the pull-up node is set to a turn-on voltage. Additionally, the shift-register circuit includes a chamfering sub-circuit coupled to the pull-up node, the first clock port, a chamfering clock port, and the output port. The chamfering sub-circuit is configured to pass a chamfering clock signal from the chamfering clock port to the output port. The chamfering clock signal is at the turn-on voltage simultaneously with the first clock signal and becomes a turn-off voltage slightly earlier in time than the first clock signal.
1. A shift-register circuit configured as one of a plurality of shift-register units, the shift-register circuit comprising:
a pull-up sub-circuit coupled to a pull-up node, a first clock port, and an output port, the pull-up sub-circuit being configured to pass a first clock signal from the first clock port to the output port when the pull-up node is set to a turn-on voltage;
a storage capacitor having a first terminal coupled to the pull-up node and a second terminal coupled to the output port; and
a chamfering sub-circuit coupled to the pull-up node, the first clock port, a chamfering clock port, and the output port, the chamfering sub-circuit being configured to pass a chamfering clock signal with the turn-on voltage from the chamfering clock port to the output port simultaneously as the first clock signal with a high voltage is provided at the first clock port and to switch off the chamfering clock signal to a turn-off voltage slightly earlier in time than the first clock signal being turned to the turn-off voltage or low voltage.
2. The shift-register circuit of claim 1 , wherein the chamfering sub-circuit comprises a first transistor coupled to a second transistor, the first transistor having a gate coupled to the first clock port, a first terminal coupled to the chamfering clock port, and a second terminal coupled to a first terminal of the second transistor; the second transistor having a gate coupled to the pull-up node, the first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the output port.
3. The shift-register circuit of claim 2 , wherein the pull-up sub-circuit comprises a third transistor having a gate coupled to the pull-up node, a first terminal coupled to the first clock port, and a second terminal coupled to the output port.
4. The shift-register circuit of claim 3 , further comprising:
an input sub-circuit coupled to the pull-up node and an input port, the input sub-circuit being configured to pass an input signal from the input port to the pull-up node;
a reset sub-circuit coupled to the pull-up node, a reset port, and a turn-off voltage port, the reset sub-circuit being configured to pass a turn-off voltage from the turn-off voltage port to the pull-up node.
5. The shift-register circuit of claim 4 , wherein the input sub-circuit comprises a fourth transistor having a gate coupled to the input port, a first terminal coupled to the input port, and a second terminal coupled to the pull-up node; the reset sub-circuit comprises a fifth transistor having a gate coupled to the reset port, a first terminal coupled to the pull-up node, and a second terminal coupled to the turn-off voltage port.
6. The shift-register circuit of claim 5 , further comprising:
a noise-control sub-circuit coupled to the pull-up node, a pull-down node, a first control port, and the turn-off voltage port, the noise-control sub-circuit being configured to pass a first control signal from the first control port to the pull-down node or to pass the turn-off voltage from the turn-off voltage port to the pull-down node depending on a voltage level at the pull-up node; and
a noise-reduction sub-circuit coupled to the pull-down node, the pull-up node, the turn-off voltage port, and the output port, the noise-reduction sub-circuit being configured to pass the turn-off voltage from the turn-off voltage port respectively to the pull-up node and the output port based on a voltage level at the pull-down node.
7. The shift-register circuit of claim 6 , wherein the noise-control sub-circuit comprises a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, wherein
the sixth transistor has a gate coupled to the pull-up node, a first terminal coupled to the pull-down node, and a second terminal coupled to the turn-off voltage port;
the seventh transistor has a gate coupled to a second terminal of the ninth transistor, a first terminal coupled to the first control port, and a second terminal coupled to coupled to the pull-down node;
the eighth transistor has a gate coupled to the pull-up node, a first terminal coupled to a second terminal of the ninth transistor, and a second terminal coupled to the turn-off voltage port; and
the ninth transistor has a gate coupled to the first control port, a first terminal coupled to the first control port;
wherein the noise-reduction sub-circuit comprises a tenth transistor and an eleventh transistor, wherein
the tenth transistor has a gate coupled to the pull-down node, a first terminal coupled to the pull-up node, and second terminal coupled to the turn-off voltage port; and
the eleventh transistor has a gate coupled to the pull-down node, a first terminal coupled to the output port, and a second terminal coupled to the turn-off voltage port.
8. The shift-register circuit of claim 7 , further comprising a pull-down sub-circuit coupled to a second control port, the output port, and the turn-off voltage port, the pull-down sub-circuit being configured to pass the turn-off voltage from the turn-off voltage port to the output port controlled by a second control signal provided to the second control port.
9. The shift-register circuit of claim 8 , wherein the pull-down sub-circuit comprises a twelfth transistor having a gate coupled to the second control port, a first terminal coupled to the output port, and a second terminal coupled to the turn-off voltage port.
10. The shift-register circuit of claim 9 , wherein each of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth transistors is an N-type transistor.
11. The shift-register circuit of claim 9 , wherein each of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth transistors is a P-type transistor.
12. A method of driving the shift-register circuit of claim 1 in an operation cycle of displaying one frame image based on signals respectively provided to an input port, a reset port, the first clock port, a chamfering port, a first control port, and a second control port, the method comprising:
in an output period of the operation cycle, providing the pull-up node with a potential level of the turn-on voltage, providing the turn-on voltage to the first clock port, providing the turn-on voltage to the chamfering clock port, and simultaneously passing the turn-on voltage from the first clock port and the chamfering clock port to the output port; and
in a chamfering period of the operation cycle, providing the pull-up node with a potential level of the turn-on voltage, providing the turn-on voltage to the first clock port, providing the turn-off voltage to the chamfering clock port, and simultaneously passing the turn-on voltage from the first clock port to the output port and passing the turn-off voltage from the chamfering clock port to the output port.
13. The method of claim 12 , wherein the operation cycle of driving the shift-register circuit comprises a scanning period including a first sub-period, a second sub-period, a third sub-period, a fourth sub-period, and a fifth sub-period, wherein during the scanning period the method comprises providing the turn-on voltage to the first control port, and providing the turn-off voltage to the second control port, providing the turn-off voltage to the turn-off voltage port.
14. The method of claim 13 , further comprising, in the first sub-period, providing the turn-on voltage to the input port, providing the turn-off voltage to the reset port, and providing the turn-off voltage to the first clock port;
in the second sub-period, providing the turn-off voltage to the input port, providing the turn-off voltage to the reset port, providing the turn-on voltage to the first clock port, and providing the turn-on voltage to the chamfering clock port, thereby passing the turn-on voltage at the first clock port and the turn-on voltage at the chamfering clock port simultaneously to the output port;
in the third sub-period, providing the turn-off voltage to the input port, providing the turn-off voltage to the reset port, providing the turn-on voltage to the first clock port, and providing the turn-off voltage to the chamfering clock port, thereby passing the turn-on voltage at the first clock port and the turn-off voltage at the chamfering clock port simultaneously to the output port;
in the fourth sub-period, providing the turn-off voltage to the input port, providing the turn-on voltage to the reset port, and providing the turn-off voltage to the first clock port; and
in the fifth sub-period, providing the turn-off voltage to the input port and providing a turn-off voltage to the reset port.
15. The method of claim 14 , wherein the operation cycle of driving the shift-register circuit further comprises a blank period.
16. The method of claim 15 , further comprising, in the blank period, providing the turn-off voltage to the first control port, providing the turn-on voltage to the second control port, and providing the turn-off voltage to the turn-off voltage port.
17. A gate-driving circuit comprising the plurality of shift-register units of claim 1 .
18. The gate-driving circuit of claim 17 , the plurality of shift-register circuits is cascaded in multiple stages from a 1st-stage to an N-th stage, wherein an output port of the shift-register circuit of an n-th stage is connected to a reset port of the shift-register circuit of a (n−1)-th stage and an input port of the shift-register circuit of the (n+1)-th stage, a first clock port of the shift-register circuit of the (n−1)-th stage is connected to a first clock signal line and a first clock port of the shift-register circuit of the n-th stage adjacent to the (n−1)-th stage is connected to a second clock signal line, where N is an integer greater than 1, and 2≤n≤N−1.
19. An array substrate comprising a gate-driving circuit of claim 17 .
20. A display apparatus comprising an array substrate of claim 19 .