Semiconductor apparatus and method for controlling semiconductor apparatus
According to one embodiment, there is provided a semiconductor apparatus including a first chip and a second chip. The first chip is electrically connected to a terminal to which a signal from a host device is input. The second chip is electrically connected to the first chip. The second chip has a first duty adjustment circuit. The first chip has a second duty adjustment circuit. The first duty adjustment circuit performs first calibration operation in a first period. The second duty adjustment circuit performs second calibration operation in a second period. The first period and the second period have an overlapping period.
1. A semiconductor apparatus comprising:
a first chip electrically connected to a terminal to which a signal from a host device is input; and
a second chip electrically connected to the first chip, wherein
the second chip has a first duty adjustment circuit,
the first chip has a second duty adjustment circuit,
the first duty adjustment circuit performs first calibration operation in a first period, the second duty adjustment circuit performs second calibration operation in a second period, and the first period and the second period have an overlapping period,
the second chip has
a data terminal,
a strobe terminal,
a first output cutoff circuit that may deactivate the data terminal, and
a second output cutoff circuit that may deactivate the strobe terminal, and
in a state in which the first output cutoff circuit deactivates the data terminal and the second output cutoff circuit deactivates the strobe terminal, the first duty adjustment circuit performs the first calibration operation, and the second duty adjustment circuit performs the second calibration operation.
2. The semiconductor apparatus according to claim 1 , wherein
the second chip further has a read enable terminal, and
in the state in which the first output cutoff circuit deactivates the data terminal and the second output cutoff circuit deactivates the strobe terminal, the first duty adjustment circuit performs the first calibration operation in the first period by means of a signal received via the read enable terminal.
3. The semiconductor apparatus according to claim 1 , further comprising:
a third chip electrically connected to the first chip, wherein
the third chip has
a third duty adjustment circuit,
a data terminal,
a strobe terminal,
a third output cutoff circuit that may deactivate the data terminal, and
a fourth output cutoff circuit that may deactivate the strobe terminal,
the second chip is electrically connected to the first chip via a first channel,
the third chip is electrically connected to the first chip via a second channel, and
in a state in which the third output cutoff circuit deactivates the data terminal and the fourth output cutoff circuit deactivates the strobe terminal, a third period in which third calibration operation is performed by the third duty adjustment circuit does not overlap with the first period.
4. The semiconductor apparatus according to claim 3 , wherein
the second chip further has a read enable terminal,
in the state in which the first output cutoff circuit deactivates the data terminal and the second output cutoff circuit deactivates the strobe terminal, the first duty adjustment circuit performs the first calibration operation in the first period by means of a signal received via the read enable terminal, and
in the state in which the third output cutoff circuit deactivates the data terminal and the fourth output cutoff circuit deactivates the strobe terminal, the third period in which the third calibration operation is performed by the third duty adjustment circuit does not overlap with the first period.
5. The semiconductor apparatus according to claim 1 , wherein
each of the first duty adjustment circuit and the second duty adjustment circuit adjusts a duty of a signal for read operation in the second chip,
the first chip further has a fourth duty adjustment circuit that adjusts a duty of a signal for write operation in the second chip,
the fourth duty adjustment circuit performs fourth calibration operation in a fourth period, and
the first period, the second period, and the fourth period have an overlapping period.
6. The semiconductor apparatus according to claim 5 , wherein
the first chip has
an interface circuit electrically connected to the second chip, and
a fifth output cutoff circuit that may electrically cut off the interface circuit from the fourth duty adjustment circuit, and
in a state in which the first output cutoff circuit deactivates the data terminal, the second output cutoff circuit deactivates the strobe terminal, and the fifth output cutoff circuit electrically cuts off the interface circuit from the fourth duty adjustment circuit, the first duty adjustment circuit performs the first calibration operation, the second duty adjustment circuit performs the second calibration operation, and the fourth duty adjustment circuit performs the fourth calibration operation.
7. The semiconductor apparatus according to claim 6 , wherein
the second chip further has a read enable terminal, and
in a state in which the first output cutoff circuit deactivates the data terminal and the second output cutoff circuit deactivates the strobe terminal, the first duty adjustment circuit performs the first calibration operation in the first period by means of a signal received via the read enable terminal.
8. The semiconductor apparatus according to claim 1 , wherein
the first duty adjustment circuit and the second duty adjustment circuit adjusts a duty of a signal for read operation in the second chip,
the first chip further has a fifth duty adjustment circuit that adjusts a duty of a strobe signal to be supplied to the host device, and
the first duty adjustment circuit performs the first calibration operation, the second duty adjustment circuit performs the second calibration operation, and the fifth duty adjustment circuit performs fifth calibration operation.
9. The semiconductor apparatus according to claim 1 , wherein
the first duty adjustment circuit and the second duty adjustment circuit adjusts a duty of a signal for read operation in the second chip,
the first chip further has
a third duty adjustment circuit that adjusts a duty of a signal for write operation in the second chip, and
a fourth duty adjustment circuit that adjusts a duty of a strobe signal to be supplied to the host device,
the fourth duty adjustment circuit performs fourth calibration operation in a fourth period, and
the first period, the second period, and the fourth period have an overlapping period.
10. The semiconductor apparatus according to claim 9 , wherein
the data terminal is a first data terminal,
the strobe terminal is a first strobe terminal,
the first output cutoff circuit may deactivate the first data terminal,
the second output cutoff circuit may deactivate the first strobe terminal,
the first chip has
a second data terminal,
a second strobe terminal,
a channel interface circuit connectable to multiple channels,
a third output cutoff circuit that may electrically cut off the channel interface circuit from the third duty adjustment circuit, and
a fourth output cutoff circuit that may electrically cut off the second strobe terminal from the fourth duty adjustment circuit, and
in a state in which the first output cutoff circuit deactivates the first data terminal, the second output cutoff circuit deactivates the first strobe terminal, the third output cutoff circuit electrically cuts off the channel interface circuit from the third duty adjustment circuit, and the fourth output cutoff circuit electrically cuts off the second strobe terminal from the fourth duty adjustment circuit, the first duty adjustment circuit performs the first calibration operation, the second duty adjustment circuit performs the second calibration operation, the third duty adjustment circuit performs third calibration operation in a third period, the fourth duty adjustment circuit performs fourth calibration operation, and the first period, the second period, the third period, and the fourth period have an overlapping period.
11. The semiconductor apparatus according to claim 10 , wherein
the second chip further has a first read enable terminal,
the first chip further has a second read enable terminal, and
in the state in which the first output cutoff circuit deactivates the first data terminal, the second output cutoff circuit deactivates the first strobe terminal, the third output cutoff circuit electrically cuts off the channel interface circuit from the third duty adjustment circuit, and the fourth output cutoff circuit electrically cuts off the second strobe terminal from the fourth duty adjustment circuit, the first duty adjustment circuit performs the first calibration operation in the first period by means of a signal received via the first read enable terminal, and the second duty adjustment circuit, the third duty adjustment circuit, and the fourth duty adjustment circuit perform the second calibration operation, the third calibration operation, and the fourth calibration operation in the first period by means of a signal received via the second read enable terminal.
12. The semiconductor apparatus according to claim 10 , wherein
the first chip further has a fifth output cutoff circuit that may electrically cut off the channel interface circuit from the second data terminal, and
in a state in which the first output cutoff circuit deactivates the first data terminal, the second output cutoff circuit deactivates the first strobe terminal, the third output cutoff circuit electrically cuts off the channel interface circuit from the third duty adjustment circuit, the fourth output cutoff circuit electrically cuts off the second strobe terminal from the fourth duty adjustment circuit, and the fifth output cutoff circuit electrically cuts off the channel interface circuit from the second data terminal, the first duty adjustment circuit performs the first calibration operation, the second duty adjustment circuit performs the second calibration operation, the third duty adjustment circuit performs the third calibration operation, the fourth duty adjustment circuit performs the fourth calibration operation, and the first period, the second period, the third period, and the fourth period have an overlapping period.
13. A method of controlling a semiconductor apparatus having a first chip electrically connected to a terminal to which a signal from a host device is input and including a second duty adjustment circuit and multiple second chips electrically connected to the first chip and including a first duty adjustment circuits, the method comprising:
performing first calibration operation in a first period by the first duty adjustment circuit; and
performing second calibration operation in a second period by the second duty adjustment circuit, wherein
the first period and the second period have an overlapping period,
the semiconductor apparatus further has a third chip electrically connected to the first chip and including a third duty adjustment circuit,
in the method, third calibration operation by the third duty adjustment circuit is further performed in a third period, and
the third period does not overlap with the first period.
14. The method according to claim 13 , wherein
each second chip has
a data terminal,
a strobe terminal,
a first output cutoff circuit that may deactivate the data terminal, and
a second output cutoff circuit that may deactivate the strobe terminal,
the performing the first calibration operation includes
performing the first calibration operation in the first period by the first duty adjustment circuit in a state in which the first output cutoff circuit deactivates the data terminal and the second output cutoff circuit deactivates the strobe terminal, and
the performing the second calibration operation includes
performing the second calibration operation in the second period by the second duty adjustment circuit in the state in which the first output cutoff circuit deactivates the data terminal and the second output cutoff circuit deactivates the strobe terminal.
15. The method according to claim 13 , wherein
the third chip has
a third duty adjustment circuit,
a data terminal,
a strobe terminal,
a third output cutoff circuit that may deactivate the data terminal, and
a fourth output cutoff circuit that may deactivate the strobe terminal,
the second chip is electrically connected to the first chip via a first channel,
the third chip is electrically connected to the first chip via a second channel, and
performing the third calibration operation includes
performing the third calibration operation in the third period by the third duty adjustment circuit in a state in which the third output cutoff circuit deactivates the data terminal and the fourth output cutoff circuit deactivates the strobe terminal.