Write operation techniques for memory systems
Methods, systems, and devices for write operation techniques for memory systems are described. In some memory systems, write operations performed on target memory cells of the memory device may disturb logic states stored by one or more adjacent memory cells. Such disturbances may cause reductions in read margins when accessing one or more memory cells, or may cause a loss of data in one or more memory cells. The described techniques may reduce aspects of logic state degradation by supporting operational modes where a host device, a memory device, or both, refrains from writing information to a region of a memory array, or inhibits write commands associated with write operations on a region of a memory array.
1. A method, comprising:
identifying, at a memory device, that a quantity of write operations performed on a region of a memory array satisfies a threshold;
setting a write mode at the memory device to refrain from applying a write signal to memory cells of the region of the memory array for a first duration based at least in part on the quantity of write operations satisfying the threshold;
receiving, at the memory device during the first duration, one or more write commands corresponding to one or more write operations from a host device;
storing, during the first duration, the one or more write commands in a buffer of the memory device based at least in part on setting the write mode at the memory device to refrain from applying the write signal to the memory cells of the region of the memory array for the first duration; and
performing the one or more write operations on the region of the memory array based at least in part on setting the write mode at the memory device to refrain from applying the write signal to the memory cells of the region for the first duration, wherein performing the one or more write operations on the region of the memory array comprises retrieving the one or more write commands from the buffer of the memory device and performing the one or more write operations after the first duration.
2. The method of claim 1 , wherein identifying that the quantity of write operations satisfies the threshold comprises:
identifying that the quantity of write operations performed during a second duration satisfies the threshold.
3. The method of claim 1 , further comprising:
determining the first duration based at least in part on a second duration over which the quantity of write operations were performed or a rate at which the quantity of write operations were performed.
4. The method of claim 1 , further comprising:
signaling, based at least in part on identifying that the quantity of write operations satisfies the threshold, an indication of the write mode for the first duration to the host device.
5. A method, comprising:
identifying, at a memory device, that a quantity of write operations performed on a region of a memory array satisfies a threshold;
refraining from writing information to the region of the memory array for a first duration based at least in part on the quantity of write operations satisfying the threshold;
performing one or more write operations on the region of the memory array based at least in part on refraining from writing information to the region for the first duration; and
permitting read operations on the region of the memory array during at least a portion of the first duration for refraining from writing information to the region of the memory array.
6. The method of claim 5 , further comprising:
receiving one or more write commands from a host device during the first duration; and
determining to perform write operations corresponding to the one or more write commands on a second region of the memory array based at least in part on refraining from writing information to the region for the first duration.
7. The method of claim 5 , wherein identifying that the quantity of write operations satisfies the threshold comprises:
identifying that the quantity of write operations performed during a second duration satisfies the threshold.
8. The method of claim 5 , further comprising:
determining the first duration based at least in part on a second duration over which the quantity of write operations were performed or a rate at which the quantity of write operations were performed.
9. The method of claim 5 , further comprising:
signaling, based at least in part on identifying that the quantity of write operations satisfies the threshold, an indication of a write mode for the first duration to a host device.
10. An apparatus, comprising:
a memory array comprising a plurality of memory cells; and
a controller operable for coupling with a host device, the controller operable to:
identify that a quantity of write operations performed on a region of the memory array satisfies a threshold;
set a write mode at the apparatus to refrain from applying a write signal to memory cells of the region of the memory array for a first duration based at least in part on the quantity of write operations satisfying the threshold;
receive, during the first duration, one or more write commands corresponding to one or more write operations from the host device;
store, during the first duration, the one or more write commands in a buffer based at least in part on setting the write mode at the apparatus to refrain from applying the write signal to the memory cells of the region of the memory array for the first duration; and
perform the one or more write operations on the region of the memory array based at least in part on setting the write mode at the apparatus to refrain from applying the write signal to the memory cells of the region of the memory array for the first duration, wherein, to perform the one or more write operations on the region of the memory array, the controller is operable to retrieve the one or more write commands from the buffer and perform the one or more write operations after the first duration.
11. The apparatus of claim 10 , wherein the controller is operable to:
determine the first duration based at least in part on a second duration over which the quantity of write operations were performed or a rate at which the quantity of write operations were performed.
12. The apparatus of claim 10 , wherein the controller is operable to:
signal, based at least in part on identifying that the quantity of write operations satisfies the threshold, an indication of the write mode for the first duration to the host device.
13. The apparatus of claim 10 , wherein each memory cell of the plurality of memory cells comprises a respective chalcogenide material element and, to refrain from applying the write signal, the controller is operable to:
refrain from applying a write current to the respective chalcogenide material element of each of the memory cells of the region of the memory array.
14. An apparatus, comprising:
a memory array comprising a plurality of memory cells; and
a controller operable to:
identify that a quantity of write operations performed on a region of the memory array satisfies a threshold;
refrain from writing information to the region of the memory array for a first duration based at least in part on the quantity of write operations satisfying the threshold;
perform one or more write operations on the region of the memory array based at least in part on refraining from writing information to the region of the memory array for the first duration; and
permit read operations on the region of the memory array during at least a portion of the first duration for refraining from writing information to the region.
15. The apparatus of claim 14 , wherein the controller is operable to:
receive one or more write commands from a host device during the first duration; and
determine to perform write operations corresponding to the one or more write commands on a second region of the memory array based at least in part on refraining from writing information to the region of the memory array for the first duration.
16. The apparatus of claim 14 , wherein the controller is operable to:
determine the first duration based at least in part on a second duration over which the quantity of write operations were performed or a rate at which the quantity of write operations were performed.
17. A method, comprising:
identifying, at a host device coupled with a memory device, that a quantity of write operations performed on a region of a memory array of the memory device satisfies a threshold;
inhibiting, at the host device and while coupled with the memory device, issuing write commands for the region of the memory array for a first duration in accordance with a write mode of the host device that is based at least in part on the quantity of write operations satisfying the threshold;
transmitting one or more read commands for one or more read operations to be performed on the region of the memory array during at least a portion of the first duration for inhibiting writing information in the region of the memory array; and
performing one or more write operations based at least in part on inhibiting issuing write commands for the region of the memory array for the first duration.
18. The method of claim 17 , further comprising:
transmitting, to the memory device, an indication that the memory device is to refrain from applying a write signal to memory cells of the region of the memory array for the first duration.
19. The method of claim 17 , wherein performing the one or more write operations comprises:
storing one or more write commands in a write buffer; and
transmitting the one or more write commands to the memory device following the first duration.
20. The method of claim 17 , further comprising:
determining to perform one or more write operations on a second region of the memory array based at least in part on inhibiting issuing write commands for the region of the memory array during the first duration; and
transmitting one or more write commands for the second region of the memory array based at least in part on determining to perform the one or more write operations on the second region of the memory array.
21. The method of claim 17 , further comprising:
determining to perform one or more write operations on a second memory device based at least in part on inhibiting issuing write commands for the region of the memory array during the first duration; and
transmitting one or more write commands to the second memory device based at least in part on determining to perform the one or more write operations on the second memory device.
22. The method of claim 17 , wherein identifying that the quantity of write operations performed on the region of the memory array satisfies the threshold comprises:
identifying that the quantity of write operations performed during a second duration satisfies the threshold.
23. The method of claim 17 , further comprising:
determining the first duration based at least in part on a second duration over which the quantity of write operations were performed or a rate at which the quantity of write operations were performed.
24. An apparatus, comprising:
a host device operable to be coupled with a memory device; and
a controller of the host device operable to:
identify that a quantity of write operations performed on a region of a memory array of the memory device satisfies a threshold;
inhibit, while coupled with the memory device, issuing write commands for the region of the memory array for a first duration in accordance with a write mode of the host device that is based at least in part on the quantity of write operations satisfying the threshold;
transmit one or more read commands for one or more read operations to be performed on the region of the memory array during at least a portion of the first duration for inhibiting writing information in the region of the memory array; and
perform one or more write operations based at least in part on inhibiting issuing write commands for the region of the memory array for the first duration.
25. The apparatus of claim 24 , wherein the controller is operable to:
transmit, to the memory device, an indication that the memory device is to refrain from applying a write signal to memory cells in the region of the memory array for the first duration.
26. The apparatus of claim 24 , wherein, to perform the write operations based at least in part on the inhibiting, the controller is operable to:
store one or more write commands in a write buffer; and
transmit the one or more write commands to the memory device following the first duration.
27. The apparatus of claim 24 , wherein the controller is operable to:
determine to perform one or more write operations on a second region of the memory array based at least in part on inhibiting issuing write commands for the region of the memory array during the first duration; and
transmit one or more write commands for the second region of the memory array based at least in part on determining to perform the one or more write operations on the second region of the memory array.
28. The apparatus of claim 24 , wherein, to perform the write operations based at least in part on the inhibiting, the controller is operable to:
determine to perform one or more write operations on a second memory device based at least in part on inhibiting issuing write commands for the region of the memory array during the first duration; and
transmit one or more write commands to the second memory device based at least in part on determining to perform the one or more write operations on the second memory device.
29. The apparatus of claim 24 , wherein, to identify that the quantity of write operations performed on the region of the memory array satisfies the threshold, the controller is operable to:
identify that the quantity of write operations performed during a second duration satisfies the threshold.
30. The apparatus of claim 24 , wherein the controller is operable to:
determine the first duration based at least in part on a second duration over which the quantity of write operations were performed or a rate at which the quantity of write operations were performed.
31. A system, comprising:
a host device; and
a memory device coupled with the host device and responsive to access commands from the host device, the memory device comprising at least one memory array having a plurality of memory cells, wherein the system is operable to:
identify, at the memory device, that a quantity of write operations performed on a region of a memory array of the memory device satisfies a threshold;
signal, from the memory device to the host device, that the region of the memory array is unavailable for write operations for a first duration based at least in part on identifying that the quantity of write operations performed on the region of the memory array satisfies the threshold;
inhibit, at the host device, issuing write commands for the region of the memory array based at least in part on receiving the signaling that the region of the memory array is unavailable for write operations for the first duration;
store one or more write commands in a write buffer of the host device based at least in part on inhibiting issuing write commands for the region of the memory array; and
transmit the one or more write commands from the host device to the memory device after the first duration.
32. The system of claim 31 , wherein the system is operable to:
determine, at the host device, to perform write operations on a second region of the memory array based at least in part on inhibiting issuing write commands for the region of the memory array; and
transmit, from the host device to the memory device, one or more second write commands for the second region of the memory array based at least in part on determining to perform write operations on the second region of the memory array.
33. The system of claim 31 , wherein the system is operable to:
determine, at the host device, to perform write operations on a second memory device based at least in part on inhibiting issuing write commands for the region of the memory array; and
transmit one or more second write commands from the host device to the second memory device based at least in part on determining to perform write operations on the second memory device.
34. The system of claim 31 , wherein the system is operable to:
determine the first duration based at least in part on a second duration over which the quantity of write operations were performed or a rate at which the quantity of write operations were performed.
35. The system of claim 31 , wherein each memory cell of the plurality of memory cells comprises a respective chalcogenide material element, and wherein, to identify that the quantity of write operations performed on the region of the memory array of the memory device satisfies the threshold, the system is operable to:
identify that a quantity of write pulses applied to chalcogenide material elements of memory cells in the region of the memory array satisfies the threshold.