IP Library Granted Patent US 11,244,948
Granted Patent B2
US 11,244,948 · App. 16/158,317 · Granted Feb 8, 2022

Semiconductor device and method of forming the same

Inventors: Feng-Yi Chang (Tainan, TW); Fu-Che Lee (Taichung, TW); Yi-Ching Chang (Pingtung County, TW); Kai-Lou Huang (New Taipei, TW)
Assignees: UNITED MICROELECTRONICS CORP.; Fujian Jinhua Integrated Circuit Co., Ltd.
H01L27/1085H01L27/10805H01L27/10873H01L27/10885H01L27/10897
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Quick Facts
Patent No.
US 11,244,948
App. No.
16/158,317
Granted
Feb 8, 2022
Kind
B2
Abstract

A semiconductor device and method of forming the same, the semiconductor device includes a substrate, a first plug, a conductive pad and a capacitor structure. The first plug is disposed on the substrate, and the conductive pad is disposed on the first plug, with the conductive pad including a recessed shoulder portion at a top corner thereof. The capacitor structure is disposed on the conductive pad, to directly in connection with thereto.

Claims (39)

1. A semiconductor device, comprising:

a substrate;

a first plug disposed on the substrate;

a bit line disposed on the substrate, wherein the bit line is disposed adjacent to the first plug;

a spacer structure between the bit line and the first plug;

a conductive pad disposed on the first plug, wherein the conductive pad is protruded from top surfaces of the bit line and the spacer structure, and the conductive pad directly contacts the top surface of the spacer structure and comprises a recessed shoulder portion at a top corner of the conductive pad; and

a capacitor structure disposed on the conductive pad, wherein a coverage area of the entire capacitor structure is completely disposed within a coverage area of the entire conductive pad in a projection direction to directly be in connection with the conductive pad, a sidewall of the capacitor structure is disposed at the recessed shoulder portion of the conductive pad, and the capacitor structure further comprises a bottom electrode and the bottom electrode fills in the recessed shoulder portion of the conductive pad.

2. The semiconductor device according to claim 1 , wherein the top corner are rounding at the recessed shoulder portion.

3. The semiconductor device according to claim 1 , wherein the recessed shoulder portion has an arc shape or a petal-like shape.

4. The semiconductor device according to claim 1 , wherein the recessed shoulder portion has a width which is about one sixth to one eighth of a width of the conductive pad.

5. The semiconductor device according to claim 1 , wherein the substrate comprises a first region and a second region, the bit line and the first plug are all disposed within the first region.

6. The semiconductor device according to claim 5 , further comprising:

a gate structure disposed on the substrate within the second region; and

a second plug disposed on the substrate within the second region, the second plug being in connection with a source/drain region disposed at two sides of the gate structure; and

another conductive pad disposed on the second plug, the another conductive pad comprising a recessed shoulder portion at a top corner of the another conductive pad.

7. The semiconductor device according to claim 1 , wherein the conductive pad and the first plug are monolithic.

8. A method of forming a semiconductor device, comprising:

providing a substrate;

forming a first plug on the substrate;

forming a bit line on the substrate, wherein the bit line is disposed adjacent to the first plug;

forming a spacer structure between the bit line and the first plug;

forming a conductive pad on the first plug, wherein the conductive pad and the first plug are monolithic to form a cross structure, and a horizontal portion of the cross structure is disposed on a top surface of the spacer structure and comprises a recessed shoulder portion at a top corner of the conductive pad; and

forming a capacitor structure on the conductive pad, wherein a coverage area of the entire capacitor structure is completely disposed within a coverage area of the entire conductive pad in a projection direction to directly connect to the conductive pad.

9. The method of forming a semiconductor device according to claim 8 , wherein forming the conductive pad further comprises:

forming a conductive layer on the substrate;

forming a patterned mask layer on the conductive layer; and

performing a first etching process through the patterned mask layer, to form an opening at a top portion of the conductive layer.

10. The method of forming a semiconductor device according to claim 9 , further comprising:

forming a spacer on sidewalls of the patterned mask layer and the opening; and

performing a second etching process through the patterned mask layer and the spacer, to form the conductive pad.

11. The method of forming a semiconductor device according to claim 10 , further comprising:

after forming the conductive pad, removing the patterned mask layer and the spacer to form the recessed shoulder portion of the conductive pad.

12. The method of forming a semiconductor device according to claim 8 , wherein forming the capacitor structure further comprises:

forming a bottom electrode to fill in the recessed shoulder portion.

13. The method of forming a semiconductor device according to claim 8 , wherein the substrate comprises a first region and a second region, the bit line and the first plug are both formed within the first region.

14. The method of forming a semiconductor device according to claim 13 , further comprising:

forming a gate structure on the substrate within the second region;

forming a second plug on the substrate within the second region, to electrically connect to a source/drain region disposed at two sides of the gate structure; and

forming another conductive pad on the second plug, the another conductive pad comprising a recessed shoulder portion at a top corner of the another conductive pad.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2018
From: CHANG, FENG-YI; LEE, FU-CHE; CHANG, YI-CHING; HUANG, KAI-LOU
To: UNITED MICROELECTRONICS CORP.; FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Reel/Frame 047144/0099 →
Priority Claims (1)
CN 201811042190.8 · Sep 7, 2018 · national
Continuity (1)
Related Publication 20200083224A1 · Mar 12, 2020