IP Library › Granted Patent US 11,245,192
Granted Patent B2
US 11,245,192 · App. 17/002,006 · Granted Feb 8, 2022

Chip antenna

Inventors: Dae Ki Lim (Suwon-si, KR); Young Sik Hur (Suwon-si, KR); Kyu Bum Han (Suwon-si, KR); Ju Hyoung Park (Suwon-si, KR); Myeong Woo Han (Suwon-si, KR); Jeong Ki Ryoo (Suwon-si, KR)
Assignee: Samsung Electro-Mechanics Co., Ltd.
H01Q9/045H01Q1/02H01Q1/2283
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Quick Facts
Patent No.
US 11,245,192
App. No.
17/002,006
Granted
Feb 8, 2022
Kind
B2
Abstract

A chip antenna includes: a first dielectric layer; a second dielectric layer upwardly spaced apart from the first dielectric layer; a patch antenna pattern disposed on the second dielectric layer; a feed via extending through the first dielectric layer; a feed pattern disposed between the first and second dielectric layers, electrically connected to the feed via, and spaced apart from the patch antenna pattern; and an adhesive layer adhered to the first and second dielectric layers. The adhesive layer includes a cavity surrounding the feed pattern between the first and second dielectric layers and; and a vent disposed between the cavity and an external side surface of the adhesive layer.

Claims (57)

1. A chip antenna, comprising:

a first dielectric layer;

a second dielectric layer upwardly spaced apart from the first dielectric layer;

a patch antenna pattern disposed on the second dielectric layer;

a feed via extending through the first dielectric layer;

a feed pattern disposed between the first and second dielectric layers, electrically connected to the feed via, and spaced apart from the patch antenna pattern; and

an adhesive layer adhered to the first and second dielectric layers, and including:

a cavity surrounding the feed pattern between the first and second dielectric layers and; and

a vent disposed between the cavity and an external side surface of the adhesive layer.

2. The chip antenna of claim 1 , wherein the adhesive layer includes a polymer having an adhesiveness higher than an adhesiveness of a dielectric material of the first and second dielectric layers.

3. The chip antenna of claim 2 , wherein the external side surface of the adhesive layer, a side surface of the first dielectric layer, and a side surface of the second dielectric layer form a single plane.

4. The chip antenna of claim 1 , wherein a width of the vent is shorter than a width of a structure surrounding the cavity on the adhesive layer.

5. The chip antenna of claim 4 ,

wherein the vent includes a plurality of vents, and

wherein at least two vents among the plurality of vents are disposed to overlap each other in a venting direction of the at least two vents.

6. The chip antenna of claim 1 , wherein the patch antenna pattern has a quadrangular shape with chamfered corners, and a side of the quadrangular shape is disposed to be diagonal to a side of the cavity.

7. The chip antenna of claim 6 , further comprising:

a plurality of coupling patterns disposed on the second dielectric layer and arranged to at least extend adjacent to sides of the quadrangular shape.

8. The chip antenna of claim 7 , wherein the patch antenna pattern and the plurality of coupling patterns are disposed on a same level on an upper surface of the second dielectric layer.

9. The chip antenna of claim 1 , wherein the patch antenna pattern is disposed on an upper surface of the second dielectric layer.

10. The chip antenna of claim 1 , wherein the feed pattern extends in a diagonal direction with respect to a side of the cavity.

11. The chip antenna of claim 1 ,

wherein at least a portion of the cavity includes air, and

wherein at least a portion of the feed pattern is plated.

12. The chip antenna of claim 1 , further comprising:

a soldering pattern disposed on a lower surface of the first dielectric layer and surrounding the feed via.

13. A chip antenna, comprising:

a first dielectric layer;

a feed via extending through the first dielectric layer;

a second dielectric layer upwardly spaced apart from the first dielectric layer;

a patch antenna pattern disposed between the first and second dielectric layers and electrically connected to the feed via; and

an adhesive layer adhered to the first and second dielectric layers, and including:

a cavity surrounding the patch antenna pattern between the first and second dielectric layers; and

a vent disposed between the cavity and an external side surface of the adhesive layer.

14. The chip antenna of claim 13 , wherein the adhesive layer includes polymer having an adhesiveness higher than an adhesiveness of a dielectric material of the first and second dielectric layers.

15. The chip antenna of claim 14 , wherein the external side surface of the adhesive layer, a side surface of the first dielectric layer, and a side surface of the second dielectric layer form a single plane.

16. The chip antenna of claim 13 , wherein a width of the vent is shorter than a width of a structure surrounding the cavity on the adhesive layer.

17. The chip antenna of claim 16 ,

wherein the vent includes four or more vents, and

wherein the patch antenna pattern has a quadrangular shape with chamfered corners, and the chamfered corners are disposed to overlap corresponding vents, among the four or more vents, in a venting direction of the corresponding vents.

18. The chip antenna of claim 13 , wherein the patch antenna pattern has a quadrangular shape having chamfered corners, and a side of the quadrangular shape is disposed to be diagonal to a side of the cavity.

19. The chip antenna of claim 13 ,

wherein at least a portion of the cavity includes air, and

wherein at least a portion of the patch antenna pattern is plated.

20. The chip antenna of claim 13 , further comprising:

a soldering pattern disposed on a lower surface of the first dielectric layer and surrounding the feed via.

21. A chip antenna, comprising:

a first dielectric layer;

a second dielectric layer disposed above the first dielectric layer;

a cavity disposed between the first dielectric layer and the second dielectric layer;

a patch antenna pattern disposed on the second dielectric layer;

a feed pattern disposed in the cavity and configured to feed a signal to or from the patch antenna pattern in a non-contact manner;

an adhesive layer attaching the first dielectric layer and the second dielectric layer to each other, and surrounding the cavity; and

a vent extending from the cavity to an external side surface of the adhesive layer.

22. The chip antenna of claim 21 , wherein the adhesive layer has a dielectric constant that is lower than a dielectric constant of the first dielectric layer and a dielectric constant of the second dielectric layer.

23. The chip antenna of claim 21 , wherein the patch antenna pattern does not extend laterally beyond the cavity.

24. The chip antenna of claim 23 , wherein the patch antenna pattern has a quadrangular shape with chamfered corners, and the vent is aligned with one of the chamfered corners.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2020
From: LIM, DAE KI; HUR, YOUNG SIK; HAN, KYU BUM; PARK, JU HYOUNG; HAN, MYEONG WOO; RYOO, JEONG KI
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 053589/0331 →
Priority Claims (1)
KR 10-2020-0040210 · Apr 2, 2020 · national
Continuity (1)
Related Publication 20210313694A1 · Oct 7, 2021