Successive Approximation Register Analog-to-Digital Converter and associated control method
View Patent ↗A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is disclosed. The SAR ADC includes a switched capacitor array, a buffer, a comparator and a control logic circuit. The switched capacitor array is arranged to sample an input signal according to a switch control signal to generate a sampling signal. The buffer is arranged to generate a common mode voltage. The comparator is arranged to receive the sampling signal and the common mode voltage in order to generate a comparison result. The control logic circuit is arranged to generate an output signal according to the comparison result, and generate the switch control signal to control the switched capacitor array. The control logic circuit further generates an operation control signal to adjust a Miller compensation capacitor inside the buffer. An associated control method is also disclosed.
1. A Successive Approximation Register Analog-to-Digital Converter (SAR ADC), comprising:
a switched capacitor array, arranged to sample an input signal according to a switch control signal to generate a sampling signal;
a buffer, arranged to generate a common mode voltage;
a comparator, arranged to receive the sampling signal and the common mode voltage in order to generate a comparison result; and
a control logic circuit, arranged to generate an output signal according to the comparison result, and generate the switch control signal to control the switched capacitor array;
wherein the control logic circuit further generates an operation control signal, to indicate that the SAR ADC operates in a sampling phase or a conversion phase, and the buffer adjusts a capacitance of a Miller compensation capacitor inside the buffer according to the operation control signal.
2. The SAR ADC of claim 1 , wherein the buffer comprises:
an amplifier, arranged to generate the common mode voltage; and
an adjustable capacitor, coupled between an input terminal and an output terminal of the amplifier, wherein the adjustable capacitor is taken as the Miller compensation capacitor.
3. The SAR ADC of claim 1 , wherein when the SAR ADC operates in the sampling phase, the capacitance of the Miller compensation capacitor inside the buffer is greater than when the SAR ADC operates in the conversion phase.
4. The SAR ADC of claim 3 , wherein the buffer comprises:
an amplifier, arranged to generate the common mode voltage; and
an adjustable capacitor, coupled between an input terminal and an output terminal of the amplifier, wherein the adjustable capacitor is taken as the Miller compensation capacitor.
5. The SAR ADC of claim 1 , wherein when the operation control signal indicates that the SAR ADC is switched from the sampling phase to the conversion phase, the buffer reduces the capacitance of the Miller compensation capacitor therein; and when the operation control signal indicates that the SAR ADC is switched from the conversion phase to the sampling phase, the buffer increases the capacitance of the Miller compensation capacitor therein.
6. The SAR ADC of claim 5 , wherein the buffer comprises:
an amplifier, arranged to generate the common mode voltage; and
an adjustable capacitor, coupled between an input terminal and an output terminal of the amplifier, wherein the adjustable capacitor is taken as the Miller compensation capacitor.
7. The SAR ADC of claim 1 , wherein when the SAR ADC operates in the sampling phase, the buffer prevents utilizing the Miller compensation capacitor.
8. The SAR ADC of claim 1 , wherein when the operation control signal indicates that the SAR ADC is switched from the sampling phase to the conversion phase, the buffer increase the capacitance of the Miller compensation capacitor therein; and when the operation control signal indicates that the SAR ADC is switched from the conversion phase to the sampling phase, the buffer prevents utilizing the Miller compensation capacitor therein.
9. A control method of a Successive Approximation Register Analog-to-Digital Converter (SAR ADC), wherein the SAR ADC comprises:
a switched capacitor array, arranged to sample an input signal according to a switch control signal to generate a sampling signal;
a buffer, arranged to generate a common mode voltage;
a comparator, arranged to receive the sampling signal and the common mode voltage in order to generate a comparison result; and
a control logic circuit, arranged to generate an output signal according to the comparison result, and generate the switch control signal to control the switched capacitor array;
wherein the control method comprises:
adjusting a Miller compensation capacitor inside the buffer according to an operation control signal, wherein the operation control signal is arranged to indicate that the SAR ADC operates in a sampling phase or a conversion phase.
10. The control method of claim 9 , wherein the step of adjusting the Miller compensation capacitor inside the buffer according to the operation control signal comprises:
when the SAR ADC operates in the sampling phase, controlling a capacitance of the Miller compensation capacitor inside the buffer to be greater than when the SAR ADC operates in the conversion phase.
11. The control method of claim 9 , wherein the step of adjusting the Miller compensation capacitor inside the buffer according to the operation control signal comprises:
when the operation control signal indicates that the SAR ADC is switched from the sampling phase to the conversion phase, reducing the capacitance of the Miller compensation capacitor inside the buffer; and
when the operation control signal indicates that the SAR ADC is switched from the conversion phase to the sampling phase, increasing the capacitance of the Miller compensation capacitor inside the buffer.
12. The control method of claim 9 , wherein the step of adjusting the Miller compensation capacitor inside the buffer according to the operation control signal comprises:
when the operation control signal indicates that the SAR ADC is switched from the sampling phase to the conversion phase, increasing the capacitance of the Miller compensation capacitor inside the buffer; and
when the operation control signal indicates that the SAR ADC is switched from the conversion phase to the sampling phase, preventing utilizing the Miller compensation capacitor inside the buffer.