Memory system with threaded transaction support
Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.
1. A method of operating a memory module, the memory module having a module substrate and first and second memory devices disposed on the module substrate, the method comprising:
buffering the first and second memory devices from a memory controller with buffer circuitry disposed on the substrate and coupled to the first and second memory devices via respective first and second secondary interfaces, the buffering including
interfacing with the memory controller via a primary signaling interface,
operating the first and second secondary interfaces at a secondary data signaling rate, and
operating the primary signaling interface at a primary data signaling rate that is at least twice the secondary data signaling rate;
transferring first column data via the first secondary interface during a first time interval;
transferring second column data via the second secondary interface during a second time interval that temporally overlaps the first time interval; and
error coding the transferred first and second column data in accordance with an error code.
2. The method according to claim 1 , wherein the transferring of the first and second column data includes:
independently accessing the first and second memory devices for concurrent data transfers of the first and second column data via the first and second secondary interfaces.
3. The method according to claim 1 , wherein the transferring of the first and second column data includes:
transferring the first and second column data in an interleaved manner at the primary signaling interface.
4. The method according to claim 1 , further comprising:
configuring the primary signaling interface to transfer data via a subset of a group of data links point-to-point between the primary signaling interface and the memory controller.
5. The method according to claim 1 , further comprising:
configuring the primary signaling interface to transfer data via all of a group of data links associated with the memory controller.
6. The method according to claim 1 , wherein:
the transferring of the first and second column data is carried out in accordance with a dynamic random access memory (DRAM) protocol.
7. The method according to claim 1 , further comprising:
during a second mode of operation, configuring the primary data signaling rate the same as the secondary data signaling rate.
8. The method according to claim 1 , further comprising:
transferring command and address signals at a first command signal rate from the memory controller to the buffer circuitry via a primary command/address (C/A/) interface;
transferring command and address signals at a second command signal rate from the buffer circuitry to the first and second memory devices via a secondary C/A interface; and
wherein the first command signal rate is at least twice the second command signal rate.
9. A method of operation in a memory system having a system substrate, and first and second memory modules coupled to the system substrate, each of the first and second memory modules including a module substrate and first and second memory devices disposed on the module substrate, the method comprising:
for each of the first and second memory modules
buffering the first and second memory devices from a memory controller with buffer circuitry disposed on the substrate and coupled to the first and second memory devices via respective first and second secondary interfaces, the buffering including
interfacing with the memory controller via a primary signaling interface,
operating the first and second secondary interfaces at a secondary data signaling rate, and
operating the primary signaling interface at a primary data signaling rate that is at least twice the secondary data signaling rate;
transferring first column data via the first secondary interface during a first time interval;
transferring second column data via the second secondary interface during a second time interval that temporally overlaps the first time interval; and
error coding the transferred first and second column data in accordance with an error code.
10. The method of claim 9 , further comprising:
interfacing a memory controller to the first and second memory modules via a group of data links.
11. The method of claim 10 , wherein:
the interfacing includes coupling the memory controller to each of the first and second memory modules via all of the group of data links in a multi-drop configuration.
12. The method of claim 10 , wherein:
the interfacing includes coupling the memory controller to each of the first and second modules via respective first and second subsets of a group of data links in a point-to-point configuration.
13. The method of claim 9 , further comprising:
transferring third column data between the memory controller and the first buffered module; and
transferring fourth column data between the memory controller and the second buffered module concurrently with transferring of the third column data.
14. The method of claim 9 , further comprising:
transferring third column data between the memory controller and the first buffered module during a time interval that does not include transferring of fourth data between the memory controller and the second buffered module.
15. A method of operation in a memory controller, the method comprising:
transferring data signals with a primary signaling interface for coupling to at least one buffered memory module via a group of data links;
dispatching command signals to the least one buffered memory module;
performing error detection/correction on the data signals transferred via the primary signaling interface; and
wherein a primary data rate of the primary signaling interface is twice a secondary data rate associated with first and second secondary interfaces of the at least one buffered memory module.
16. The method according to claim 15 , wherein:
the transferring data signals with the primary signaling interface comprises coupling to each of the at least one buffered memory modules in a point-to-point configuration.
17. The method according to claim 15 , wherein:
the transferring data signals with the primary signaling interface comprises coupling to each of the at least one buffered memory modules in a multi-drop configuration.
18. The method according to claim 15 , wherein:
during a second mode of operation, the primary data rate of the primary signaling interface is the same as the secondary data rate of the first and second secondary interfaces of the at least one buffered memory module.
19. The method according to claim 15 , wherein:
the dispatching command signals includes transferring the command signals to access first and second memory devices on the at least one buffered memory module independently for concurrent data transfers of first and second data via the first and second secondary interfaces.
20. The method according to claim 16 , wherein:
the transferring of the data signals is carried out in accordance with a dynamic random access memory (DRAM) protocol.