Non-volatile storage circuitry accessible as primary storage for processing circuitry

1. An apparatus comprising:

processing circuitry to perform data processing in response to instructions;

non-volatile storage circuitry accessible by the processing circuitry as primary storage; and

power control circuitry to power down a given region of the non-volatile storage circuitry when information stored in said given region is not being used, in which:

the non-volatile storage circuitry comprises a plurality of hardware thread storage regions each to store context information associated with a corresponding one of a plurality of hardware threads; and the processing circuitry is configured to process instructions from at least one active thread selected from among said plurality of hardware threads; or

in response to a stall event occurring during processing of instructions from a given thread, the power control circuitry is configured to power down at least part of a region of the non-volatile storage circuitry which stores information associated with the given thread; or

the processing circuitry is configured to process instructions in one of a plurality of operating states; and when the processing circuitry is processing instructions in a current operating state, the power control circuitry is configured to power down a region of the non-volatile storage circuitry for storing information associated with at least one operating state other than the current operating state; or

the non-volatile storage circuitry comprises registers to store architectural state of the processing circuitry; and in response to a thread or a portion of a thread which does not require a subset of the architectural state, the power control circuitry is configured to power down a region of the non-volatile storage for storing the subset of the architectural state.

2. The apparatus according to claim 1 , in which the processing circuitry is configured to directly obtain operands for execution of said instructions from said non-volatile storage circuitry and to directly store results of said instructions to said non-volatile storage circuitry.

3. The apparatus according to claim 1 , in which when powering down the given region of the non-volatile storage circuitry, the power control circuitry is configured to omit saving of information stored in the given region to a powered up storage region or to secondary storage.

4. The apparatus according to claim 1 , in which the processing circuitry is configured to use the non-volatile storage circuitry as at least one of:

registers to store architectural state of the processing circuitry;

a cache;

a scratchpad memory; and

random access memory serving as primary storage;

a prediction structure to store prediction state used to control speculative execution of instructions by the processing circuitry.

5. The apparatus according to claim 1 , in which the power control circuitry is configured to control, on a cycle by cycle basis, whether the given region of the non-volatile storage circuitry is in a power up state or a power down state.

6. The apparatus according to claim 1 , in which the processing circuitry is configured to process instructions from a plurality of threads; and

the non-volatile storage circuitry comprises a plurality of thread-specific storage regions each to store information associated with a corresponding thread of the plurality of threads.

7. The apparatus according to claim 6 , in which:

when processing a plurality of active threads including a given thread, the thread-specific storage region associated with the given thread is accessible to the given thread and inaccessible to active threads other than the given thread; and

when processing a supervisory process for supervising the given thread, the thread-specific storage region associated with the given thread is accessible.

8. The apparatus according to claim 6 , comprising a shared storage region of the primary storage accessible to more than one of the plurality of threads.

9. The apparatus according to claim 6 , in which the power control circuitry is configured to control the given thread-specific storage region associated with a given thread to be in a power down state in a cycle when none of a plurality of power up conditions is satisfied;

said plurality of power up conditions including at least:

the given thread or a supervisory process requiring access to the given thread-specific storage region; and

information to be written to the given thread-specific storage region being returned in response to a memory access initiated in an earlier cycle.

10. The apparatus according to claim 6 , in which the non-volatile storage circuitry comprises a cache comprising said plurality of thread-specific storage regions; and

on powering down a given thread-specific storage region of the cache, when the given thread-specific storage region includes dirty information, the power control circuitry is configured to omit writing back the dirty information to memory.

11. The apparatus according to claim 6 , in which the non-volatile storage circuitry comprises a cache comprising said plurality of thread-specific storage regions; and

in response to a memory access request issued by another processing element other than the processing circuitry, when the request specifies an address corresponding to information in a given thread-specific storage region of the cache which is powered down, the power control circuitry is configured to power up the thread-specific storage region to allow the request to be serviced.

12. The apparatus according to claim 1 , in which in response to the stall event occurring during processing of instructions from the given thread, the power control circuitry is configured to power down the at least part of the region of the non-volatile storage circuitry which stores the information associated with the given thread, and the stall event comprises at least one of:

a memory access requiring latency longer than a given threshold;

a miss in a given level of cache;

a memory access which requires access to data stored in secondary storage;

an event indicative of the given thread waiting for a synchronisation variable to indicate that the given thread is allowed to access a shared variable for which exclusive access to the shared variable is controlled based on the synchronisation variable;

an event indicative of the given thread waiting for a message to be received from another thread or external device; and

execution of a wait-for-event instruction by the given thread.

13. The apparatus according to claim 1 , in which the non-volatile storage circuitry comprises the registers to store the architectural state of the processing circuitry; and when, in response to the thread or the portion of the thread which does not require the subset of the architectural state, the power control circuitry is configured to power down the region of the non-volatile storage for storing the subset of the architectural state, and the subset of the architectural state comprises at least one of:

floating-point register state comprising floating-point values or floating-point control state for controlling processing of the floating-point values; and

vector register state comprising vector values or vector control state for controlling processing of the vector values;

control register state to initialize and control system functions;

status register state comprising indications of historical events; and

control register state comprising control information of an operating state other than the current operating state.

14. The apparatus according to claim 13 , in which the power control circuitry is configured to determine whether said thread or said portion of the thread requires said subset of architectural state based on at least one of:

hint information specified by program code for said thread or said portion of the thread; and

monitoring information collected by monitoring circuitry on a previous instance of executing said thread or said portion of the thread.

15. A data processing method comprising:

performing data processing in response to instructions, using processing circuitry;

accessing non-volatile storage circuitry as primary storage of the processing circuitry; and

powering down a given region of the non-volatile storage circuitry when information stored in said given region is not being used; in which:

the non-volatile storage circuitry comprises a plurality of hardware thread storage regions each to store context information associated with a corresponding one of a plurality of hardware threads; and the processing circuitry processes instructions from at least one active thread selected from among said plurality of hardware threads; or

in response to a stall event occurring during processing of instructions from a given thread, the method comprises powering down at least part of a region of the non-volatile storage circuitry which stores information associated with the given thread; or

the processing circuitry is configured to process instructions in one of a plurality of operating states; and when the processing circuitry is processing instructions in a current operating state, the method comprises powering down a region of the non-volatile storage circuitry for storing information associated with at least one operating state other than the current operating state; or

the non-volatile storage circuitry comprises registers to store architectural state of the processing circuitry; and the method comprises, in response to a thread or a portion of a thread which does not require a subset of the architectural state, powering down a region of the non-volatile storage for storing the subset of the architectural state.

16. An apparatus comprising:

processing circuitry to perform data processing in response to instructions;

non-volatile storage circuitry accessible by the processing circuitry as primary storage; and

power control circuitry to power down a given region of the non-volatile storage circuitry when information stored in said given region is not being used, in which the processing circuitry is configured to process instructions from a plurality of threads; and

the non-volatile storage circuitry comprises a plurality of thread-specific storage regions each to store information associated with a corresponding thread of the plurality of threads, in which:

when processing a plurality of active threads including a given thread, the thread-specific storage region associated with the given thread is accessible to the given thread and inaccessible to active threads other than the given thread; and when processing a supervisory process for supervising the given thread, the thread-specific storage region associated with the given thread is accessible; or

the non-volatile storage circuitry comprises a cache comprising said plurality of thread-specific storage regions; and on powering down a given thread-specific storage region of the cache, when the given thread-specific storage region includes dirty information, the power control circuitry is configured to omit writing back the dirty information to memory; or

the non-volatile storage circuitry comprises a cache comprising said plurality of thread-specific storage regions; and in response to a memory access request issued by another processing element other than the processing circuitry, when the request specifies an address corresponding to information in a given thread-specific storage region of the cache which is powered down, the power control circuitry is configured to power up the thread-specific storage region to allow the request to be serviced; or

the power control circuitry is configured to control the given thread-specific storage region associated with a given thread to be in a power down state in a cycle when none of a plurality of power up conditions is satisfied; said plurality of power up conditions including at least:

the given thread or a supervisory process requiring access to the given thread-specific storage region; and

information to be written to the given thread-specific storage region being returned in response to a memory access initiated in an earlier cycle.

17. The apparatus according to claim 16 , comprising a shared storage region of the primary storage accessible to more than one of the plurality of threads.