Targeted command/address parity low lift
Methods, systems, and devices for targeted command/address parity low lift are described. A memory device may receive a command (e.g., a write command or a read command) from a host device over a first set of pins and may perform data transfer over a second set of pins with the host device during a set of time intervals according to the command. The memory device may exchange a parity bit associated with the command with the host device over a third set of pins during a first time intervals of the set of time intervals. In some cases, the third memory device may exchange at least one additional bit associated with the command with the host device during at least one time interval of the set of time intervals.
1. A method, comprising:
receiving a write command from a host device via a first set of pins;
receiving data from the host device during a plurality of time intervals via a second set of pins based at least in part on receiving the write command;
receiving a first parity bit associated with the write command via a third set of pins during a first time interval of the plurality of time intervals, wherein the third set of pins is used to receive at least one additional bit associated with the write command during at least one time interval of the plurality of time intervals;
generating a second parity bit based at least in part on the write command; and
generating a parity result bit based at least in part on comparing the first parity bit and the second parity bit.
2. The method of claim 1 , further comprising:
receiving an error correction code for the data comprising the at least one additional bit via the third set of pins during a second time interval of the plurality of time intervals.
3. The method of claim 2 , further comprising:
receiving encoding information via a fourth set of pins for the data during the first time interval; and
receiving a second error correction code via the third set of pins for the encoding information during a third time interval of the plurality of time intervals.
4. The method of claim 3 , wherein the first parity bit is received prior to the second error correction code.
5. The method of claim 2 , wherein the first parity bit is received prior to the error correction code for the data.
6. The method of claim 1 , further comprising:
receiving a read command from the host device via the first set of pins subsequent to receiving the write command; and
transmitting the parity result bit to the host device via the third set of pins based at least in part on receiving the read command.
7. The method of claim 1 , further comprising:
receiving a read command from the host device via the first set of pins; and
transmitting a redundant data strobe signal via the third set of pins based at least in part on receiving the read command.
8. The method of claim 1 , wherein each time interval of the plurality of time intervals is a cycle or a portion of a cycle of a clock signal.
9. The method of claim 1 , wherein a first portion of the write command is received over a first subset of the first set of pins for receiving a command and wherein a second portion of the write command is received over a second subset of the first set of pins for receiving an address, and wherein the first parity bit is for the first portion of the write command, the second portion of the write command, or both.
10. A method, comprising:
receiving a read command from a host device via a first set of pins;
transmitting data to the host device during a plurality of time intervals via a second set of pins based at least in part on receiving the read command;
generating a parity bit based at least in part on the read command; and
transmitting the parity bit associated with the read command via a third set of pins during a first time interval of the plurality of time intervals, wherein the third set of pins is used to transmit at least one additional bit associated with the read command during at least one time interval of the plurality of time intervals.
11. The method of claim 10 , further comprising:
transmitting an error correction code for the data comprising the at least one additional bit via the third set of pins during a second time interval of the plurality of time intervals.
12. The method of claim 11 , wherein the parity bit is transmitted prior to transmitting the error correction code for the data.
13. The method of claim 11 , further comprising:
transmitting an indication of a data set function via the third set of pins during a third time interval of the plurality of time intervals.
14. The method of claim 13 , wherein the parity bit is transmitted prior to transmitting the indication of the data set function.
15. The method of claim 10 , further comprising:
receiving a write command from the host device via the first set of pins; and
receiving a data mask signal via the third set of pins based at least in part on receiving the write command.
16. The method of claim 10 , wherein a first portion of the read command is received over a first subset of the first set of pins for receiving a command and wherein a second portion of the read command is received over a second subset of the first set of pins for receiving an address, and wherein the parity bit is for the first portion of the read command, the second portion of the read command, or both.
17. A memory device, comprising:
a first set of pins configured to receive a command from a host device;
a second set of pins configured to perform data transfer with the host device during a plurality of time intervals; and
a third set of pins configured to exchange a parity bit associated with the command with the host device during a first time interval of the plurality of time intervals, and wherein the third set of pins is further configured to exchange at least one additional bit associated with the command with the host device during at least one time interval of the plurality of time intervals.
18. The memory device of claim 17 , wherein the third set of pins is further configured to exchange an error correction code for the data comprising the at least one additional bit with the host device during a second time interval of the plurality of time intervals.
19. The memory device of claim 18 , wherein the parity bit is exchanged with the host device prior to exchanging the error correction code for the data.
20. The memory device of claim 17 , wherein the memory device further comprises a fourth set of pins configured to exchange encoding information for the data with the host device during the first time interval of the plurality of time intervals.
21. The memory device of claim 17 , wherein the command is a write command, and wherein the third set of pins is configured to receive the parity bit based at least in part on the command being the write command.
22. The memory device of claim 17 , wherein the command is a read command, and wherein the third set of pins is configured to transmit the parity bit based at least in part on the command being the read command.
23. The memory device of claim 17 , wherein the memory device is a dynamic random-access memory.