Semiconductor device and method of controlling self-diagnosis
A semiconductor device capable of suppressing a sharp change in current consumption and a self-diagnosis control method thereof are provided. According to one embodiment, the semiconductor device 1 includes a logic circuit, which is a circuit to be diagnosed, a self-diagnostic circuit for diagnosing the logic circuit, and a diagnostic control circuit for controlling the diagnosis of the logic circuit by the self-diagnostic circuit, and the diagnostic control circuit includes a diagnostic abort control circuit for gradually stopping the diagnosis of the logic circuit by the self-diagnostic circuit when the semiconductor device receives a stop signal instructing the stop of the diagnosis of the logic circuit by the self-diagnostic circuit.
1. A semiconductor device comprising:
a circuit to be diagnosed;
a self-diagnostic circuit that diagnoses the circuit to be diagnosed; and
a diagnostic control circuit that controls the diagnosis of the circuit to be diagnosed by the self-diagnostic circuit, wherein a test clock is supplied to the circuit under diagnosis,
wherein the diagnostic control circuit includes:
a diagnostic abort control circuit that, when an abort signal indicating the abort of the diagnosis of the circuit to be diagnosed by the self-diagnostic circuit is received, aborts the diagnosis of the circuit to be diagnosed by the self-diagnostic circuit before stopping supplying the test clock to the circuit under diagnosis such that the diagnosis of the circuit is aborted while the test clock continues to be supplied to the circuit.
2. The semiconductor device according to claim 1 , wherein the diagnostic abort control circuit is configured to, when receiving the abort signal during a period in which a test operation of the circuit under diagnosis is being performed by supplying a test pattern, cause the self-diagnostic circuit to perform a cool-down process of the test operation of the circuit under diagnosis, and then gradually decrease a frequency of the test clock supplied to the circuit under diagnosis.
3. The semiconductor device according to claim 2 , wherein the diagnostic abort control circuit is configured to gradually decrease the frequency of the test clock supplied to the circuit under diagnosis together with the test pattern to a predetermined frequency in the cool-down process.
4. The semiconductor device according to claim 2 ,
wherein the self-diagnostic circuit includes a plurality of test pattern generation circuits each generating the test pattern, and
wherein the diagnostic abort control circuit is configured to sequentially halt the generation of test patterns by the plurality of test pattern generation circuits in the cool-down process.
5. The semiconductor device according to claim 1 , wherein the diagnostic abort control circuit is configured to gradually decrease a frequency of the test clock supplied to the circuit under diagnosis after completion of a cool-down process when the abort signal is received during a period in which the cool-down process of a test operation of the circuit under diagnosis is performed.
6. The semiconductor device according to claim 1 , wherein the diagnostic abort control circuit is configured to gradually decrease a frequency of a test clock supplied to the circuit under diagnosis when the abort signal is received during a period in which the self-diagnostic circuit sets a start of supplying the test clock to the circuit under diagnosis.
7. The semiconductor device according to claim 6 , wherein the diagnostic abort control circuit is configured to gradually decrease the frequency of the test clock supplied to the circuit under diagnosis after setting of starting the supply of the test clock is completed.
8. The semiconductor device according to claim 1 , wherein the diagnostic abort control circuit is configured to gradually decrease a frequency of the test clock supplied to the circuit under diagnosis when the abort signal is received in any of a period from a completion of setting of a start of supply of the test clock to the circuit under diagnosis by the self-diagnostic circuit to a start of a test operation of the circuit under diagnosis by the self-diagnostic circuit, a period during which a determination of a result of a test operation of the circuit under diagnosis is performed, and a period during which stopping the supply of the test clock to the circuit under diagnosis is performed.
9. The semiconductor device according to claim 1 , wherein when the diagnostic abort control circuit receives the abort signal either during a period in which a test operation of the circuit under diagnosis is being performed by being supplied with a test pattern, or during a period in which a cool-down process of a test operation of the circuit under diagnosis is being performed, after a completion of a cool-down process of the test operation of the circuit under diagnosis, a mode is switched from a self-diagnosis mode to a normal operation mode without further decreasing a frequency of the test clock supplied to the circuit under diagnosis after completion of the cool-down process.
10. The semiconductor device according to claim 1 , wherein the diagnostic abort control circuit is configured to, upon receiving the abort signal, gradually halt the diagnosis of the circuit under diagnosis by the self-diagnostic circuit by waiting for the diagnosis of the circuit under diagnosis by the self-diagnostic circuit to be completed.
11. The semiconductor device according to claim 1 , wherein the abort signal is a reset signal.
12. A method of controlling self-diagnosis of a semiconductor device, the method comprising:
diagnosing a circuit to be diagnosed by a self-diagnostic circuit, wherein a test clock is supplied to the circuit under diagnosis; and
when an abort signal indicating the abort of the diagnosis of the circuit to be diagnosed by the self-diagnostic circuit is received, aborting the diagnosis of the circuit to be diagnosed by the self-diagnostic circuit before stopping supplying the test clock to the circuit under diagnosis such that the diagnosis of the circuit is aborted while the test clock continues to be supplied to the circuit.