Semiconductor system and method for operating semiconductor system for reducing time to perform initialization of a universal flash storage (UFS) host
Provided is a semiconductor system. The semiconductor system includes a universal flash storage (UFS) host, including a host controller interface, a UniPro and a M-PHY; a UFS device configured to exchange data with the UFS host through a UFS interface; and an application processor configured to control the UFS host. The UFS device is configured to maintain a power-on status when the application processor operates in a suspend mode.
1. A semiconductor system, comprising:
a universal flash storage (UFS) host comprising a host controller interface, a Unified Protocol (UniPro) interface and a M-PHY interface;
a UFS device configured to exchange data with the UFS host through a UFS interface; and
an application processor configured to control the UFS host,
wherein the UFS device is configured to maintain a power-on status when the application processor operates in a suspend mode, and
wherein after the application processor exits the suspend mode, the UFS host is configured not to perform a UFS Linkstartup task.
2. The semiconductor system of claim 1 , wherein the UFS device is configured to operate in a hibernation mode when the application processor operates in the suspend mode.
3. The semiconductor system of claim 2 , wherein the application processor is configured to provide a reference clock signal to the UFS device before the UFS device enters the hibernation mode, and the application processor is configured not to provide the reference clock signal to the UFS device when the UFS device operates in the hibernation mode.
4. The semiconductor system of claim 2 , wherein the application processor is configured to provide a reset signal to the UFS device when the application processor operates in the suspend mode.
5. The semiconductor system of claim 2 , wherein before the application processor enters the suspend mode, the UFS device is configured to enter the hibernation mode.
6. The semiconductor system of claim 5 , wherein before the UFS device enters the hibernation mode, the application processor is configured to store at least one of a setting value or status information relating to at least one of the host controller interface, the Unified Protocol (UniPro) interface, or the M-PHY interface of the UFS host.
7. The semiconductor system of claim 2 , wherein after the application processor exits the suspend mode, the UFS device is configured to exit the hibernation mode.
8. The semiconductor system of claim 7 , wherein before the UFS device exits the hibernation mode, the application processor is configured to restore at least one of a setting value or status information relating to the at least one of the host controller interface, the Unified Protocol (UniPro) interface, or the M-PHY interface of the UFS host.
9. The semiconductor system of claim 1 , wherein after the application processor exits the suspend mode, the UFS host is further configured not to perform a UFS Power Mode Change task.
10. A semiconductor system, comprising:
a universal flash storage (UFS) host comprising a host controller interface, a Unified Protocol (UniPro) interface and a M-PHY interface;
a UFS device configured to exchange data with the UFS host through a UFS interface; and
an application processor configured to control the UFS host,
wherein the UFS device is configured to maintain a power-on status when the UFS host is in a power-off status.
11. The semiconductor system of claim 10 , wherein the UFS device is configured to operate in a hibernation mode when the UFS host is in the power-off status.
12. The semiconductor system of claim 11 , wherein the application processor is configured to provide a reference clock signal to the UFS device before the UFS device enters the hibernation mode, and the application processor is configured not to provide the reference clock signal to the UFS device when the UFS device operates in the hibernation mode.
13. The semiconductor system of claim 11 , wherein when the UFS host is in the power-off status, the application processor is configured to provide a reset signal to the UFS device.
14. A method for operating a semiconductor system, the method comprising:
storing, by an application processor, at least one of a setting value or status information relating to at least one of a host controller interface, a Unified Protocol (UniPro) interface or a M-PHY interface of a universal flash storage (UFS) host;
entering, by an UFS device, a hibernation mode;
controlling, by the application processor, the UFS host to enter a suspend mode;
exiting, by the application processor, the suspend mode;
restoring, by the application processor, the at least one of the setting value or the status information relating to the at least one of the host controller interface, the Unified Protocol (UniPro) interface or the M-PHY interface of the UFS host; and
exiting, by the UFS device, the hibernation mode,
wherein after the application processor exits the suspend mode, the UFS host is configured not to perform a UFS Linkstartup task.
15. The method for operating the semiconductor system of claim 14 , wherein the UFS device is configured to operate in the hibernation mode when the application processor operates in the suspend mode.
16. The method for operating the semiconductor system of claim 15 , wherein the application processor is configured to provide a reference clock signal to the UFS device before the UFS device enters the hibernation mode, and the application processor is configured not to provide the reference clock signal to the UFS device when the UFS device operates in the hibernation mode.
17. The method for operating the semiconductor system of claim 15 , wherein the application processor is configured to provide a reset signal to the UFS device.
18. The method for operating the semiconductor system of claim 14 , wherein after the application processor exits the suspend mode, the UFS host is further configured not to perform a UFS Power Mode Change task.