Multiple mode arithmetic circuit
A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.
1. A circuit comprising:
a mode selection input that selects a mode from a set of modes comprising a first mode and a second mode;
a plurality of integer arithmetic logic blocks; and
a circuit portion that converts an output from the plurality of integer arithmetic logic blocks to a floating-point number in the second mode;
wherein:
in the first mode, the plurality of integer arithmetic logic blocks is configured to perform operations on integer operands;
in the second mode, the plurality of integer arithmetic logic blocks is configured to perform operations on floating-point operands; and
the conversion comprises:
determining, in parallel, two candidate exponent values of the floating-point number;
estimating a count of leading zeroes in the output; and
selecting between the two candidate exponent values based on a determination of whether the estimated count of leading zeroes is correct.
2. The circuit of claim 1 , further comprising:
a set of input connections; and
bit remapping circuitry that selectively connects the input connections to the integer arithmetic logic blocks based on the mode selection input, the bit remapping circuitry being operable in both the first mode and the second mode.
3. The circuit of claim 2 , further comprising:
interconnection circuitry among the plurality of integer arithmetic logic blocks, the interconnection circuitry comprising a plurality of registers and multiplexers, the registers and multiplexers being operable in both the first mode and the second mode.
4. The circuit of claim 1 , wherein:
in the second mode, the floating-point operands comprise a first operand and a second operand; and
the performing of operations on the floating-point operands comprises shifting a mantissa of the second operand by a difference between an exponent of the first operand and an exponent of the second operand based on a determination that the exponent of the first operand is the greatest exponent among exponents of the floating-point operands.
5. The circuit of claim 1 , wherein:
the floating-point operands are of a first format;
the set of modes further comprises a third mode;
in the third mode, the plurality of integer arithmetic logic blocks is configured to perform operations on second floating-point operands of a second format;
the performing of operations on the floating-point operands of the first format comprises converting the floating-point operands to a third format; and
the performing of operations on the second floating-point operands of the second format comprises converting the second floating-point operands to the third format.
6. The circuit of claim 5 , wherein the third format comprises a fifteen-bit mantissa, a one-bit sign, and an eight-bit exponent.
7. The circuit of claim 5 , wherein:
a mantissa size of the third format is greater than or equal to a mantissa size of the first format;
the mantissa size of the third format is greater than or equal to a mantissa size of the second format; and
the mantissa size of the second format is different from the mantissa size of the first format.
8. The circuit of claim 1 , further comprising:
an adder that generates a result that is a sum of partial products.
9. The circuit of claim 1 , wherein:
the integer operands are of a first size;
the operations on the integer operands are a first number of operations on the integer operands;
the set of modes further comprises a third mode; and
in the third mode, the plurality of integer arithmetic logic blocks is configured to perform a second number of operations on second integer operands of a second size, the second size being larger than the first size, the second number of operations being smaller than the first number of operations.
10. The circuit of claim 9 , wherein:
the first size is eight bits;
the second size is sixteen bits; and
the first number of operations is four times the second number of operations.
11. The circuit of claim 1 , further comprising:
a plurality of output connections that, in the first mode and the second mode, provide a plurality of partial products, wherein a bit width of each partial product is based on a number of partial products provided.
12. A non-transitory machine-readable medium containing instructions that, when executed by one or more processors, cause the one or more processors to control configuration of a field programmable gate array (FPGA) comprising:
a mode selection input that selects a mode from a set of modes comprising a first mode and a second mode; and
a plurality of integer arithmetic logic blocks; and
a circuit portion that converts an output from the plurality of integer arithmetic logic blocks to a floating-point number in the second mode;
wherein:
in the first mode, the plurality of integer arithmetic logic blocks is configured to perform operations on integer operands;
in the second mode, the plurality of integer arithmetic logic blocks is configured to perform operations on floating-point operands; and
the conversion comprises:
determining, in parallel, two candidate exponent values of the floating-point number;
estimate a count of leading zeroes in the output; and
selecting between the two candidate exponent values based on a determination of whether the estimated count of leading zeroes is correct.
13. The non-transitory machine-readable medium of claim 12 , wherein the FPGA further comprises:
a set of input connections; and
bit remapping circuitry that selectively connects the input connections to the integer arithmetic logic blocks based on the mode selection input, the bit remapping circuitry being operable in both the first mode and the second mode.
14. The non-transitory machine-readable medium of claim 13 , wherein the FPGA further comprises:
interconnection circuitry among the plurality of integer arithmetic logic blocks, the interconnection circuitry comprising a plurality of registers and multiplexers, the registers and multiplexers being operable in both the first mode and the second mode.
15. The non-transitory machine-readable medium of claim 12 , wherein:
in the second mode, the floating-point operands comprise a first operand and a second operand; and
the performing of operations on the floating-point operands comprises shifting a mantissa of the second operand by a difference between an exponent of the first operand and an exponent of the second operand based on a determination that the exponent of the first operand is the greatest exponent among exponents of the floating-point operands.
16. The non-transitory machine-readable medium of claim 12 , wherein:
the floating-point operands are of a first format;
the set of modes further comprises a third mode;
in the third mode, the plurality of arithmetic logic blocks is configured to perform operations on second floating-point operands of a second format;
the performing of operations on the floating-point operands of the first format comprises converting the floating-point operands to a third format; and
the performing of operations on the second floating-point operands of the second format comprises converting the second floating-point operands to the third format.
17. The non-transitory machine-readable medium of claim 16 , wherein the third format comprises a fifteen-bit mantissa, a one-bit sign, and an eight-bit exponent.
18. The non-transitory machine-readable medium of claim 16 , wherein:
a mantissa size of the third format is greater than or equal to a mantissa size of the first format;
the mantissa size of the third format is greater than or equal to a mantissa size of the second format; and
the mantissa size of the second format is different from the mantissa size of the first format.
19. The non-transitory machine-readable medium of claim 12 , wherein the FPGA further comprises:
a plurality of output connections that, in the first mode and the second mode, provide a plurality of partial products, wherein a bit width of each partial product is based on a number of partial products provided.
20. A method comprising:
receiving, by a circuit, a mode selection input that selects a mode from a set of modes comprising a first mode and a second mode; and
based on the selected mode:
configuring a plurality of integer arithmetic logic blocks to perform operations on floating-point operands; and
converting an output from the plurality of integer arithmetic logic blocks to a floating-point number, the converting comprising:
determining in parallel, two candidate exponent values of the floating-point number:
estimating a count of leading zeroes in the output; and
selecting between the two candidate exponent values based on a determination of whether the estimated count of leading zeroes is correct.