Mitigation of return-oriented programming exploits

1. A computing apparatus, comprising:

a processor;

a memory; and

encoded logic to instruct the processor to:

identify within the memory a payload that is suspected to be a return-oriented programming (ROP) chain;

execute the suspected ROP chain in a speculative execution path within the processor;

force a missed prediction of the speculative execution path;

determine that the suspected ROP chain executed through, comprising determining that a canary instruction appended to the suspected ROP chain was executed; and

take a security action responsive to the determining.

2. The computing apparatus of claim 1 , wherein executing the suspected ROP chain the speculative execution path comprises populating a stack return register with a pointer to the suspected ROP chain.

3. The computing apparatus of claim 1 , wherein the canary instruction comprises a dummy label.

4. The computing apparatus of claim 1 , wherein the canary instruction comprises a load from a memory address.

5. The computing apparatus of claim 4 , wherein determining that the suspected ROP chain executed through comprises determining that the memory address of the canary instruction is located in cache.

6. The computing apparatus of claim 4 , wherein determining that the suspected ROP chain executed through comprises loading the address of the canary instruction, and measuring the time for loading the address to complete.

7. The computing apparatus of claim 4 , wherein determining that the suspected ROP malware is malicious comprises determining that the label was loaded to cache.

8. The computing apparatus of claim 5 , wherein determining that the label was loaded to cache comprises determining a latency to fetch the label.

9. The computing apparatus of claim 6 , wherein the logic is further to perform a cache flash before executing the suspected ROP chain.

10. The computing apparatus of claim 1 , further comprising encoded logic to force an increased latency on a speculative execution window.

11. The computing apparatus of claim 10 , wherein forcing the increased latency comprises adding memory access latency.

12. One or more tangible, non-transitory computer-readable mediums having stored thereon executable instructions to:

dynamically scan a binary object to identify a potential return-oriented programming (ROP) chain;

append a canary instruction to the end of the potential ROP chain;

execute the potential ROP chain within a speculative execution path, and force a missed prediction;

determine that the canary instruction was executed; and

based at least in part on the determining, designate the potential ROP chain as an ROP chain.

13. The one or more tangible, non-transitory computer-readable mediums of claim 12 , wherein the instructions are further to take a security action based on the designating.

14. The one or more tangible, non-transitory computer-readable mediums of claim 12 , wherein the canary instruction comprises a dummy label.

15. A computer-implemented method of detecting a return-oriented programming (ROP) exploit, comprising:

appending a dummy instruction to the end of a suspected ROP chain;

executing the suspected ROP chain within a speculative execution path that does not affect an architectural state on a missed prediction;

determining that the dummy instruction was executed; and

designating the suspected ROP chain as an ROP chain.

16. The method of claim 15 , further comprising taking a security action based on the designating.

17. The one or more tangible, non-transitory computer-readable mediums of claim 12 , wherein the canary instruction comprises a load from a memory address.

18. The one or more tangible, non-transitory computer-readable mediums of claim 17 , wherein determining that the suspected ROP chain executed through comprises determining that the memory address of the canary instruction is located in cache.

19. The method of claim 15 , wherein the dummy instruction comprises a dummy label.

20. The method of claim 15 , wherein the dummy instruction comprises a load from a memory address.

21. The method of claim 20 , wherein determining that the suspected ROP chain executed through comprises determining that the memory address of the dummy instruction is located in cache.