IP Library Granted Patent US 11,257,625
Granted Patent B2
US 11,257,625 · App. 16/654,053 · Granted Feb 22, 2022

Multilayer ceramic capacitor

Inventors: Yuichiro Yao (Nagaokakyo, JP); Keisuke Fukumura (Nagaokakyo, JP)
Assignee: MURATA MANUFACTURING CO., LTD.
H01G4/30C04B35/4682H01G4/008H01G4/1209H01G4/232C04B2235/5445C04B2235/785
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Quick Facts
Patent No.
US 11,257,625
App. No.
16/654,053
Granted
Feb 22, 2022
Kind
B2
Abstract

A multilayer ceramic capacitor includes a multilayer body in which a plurality of internal electrodes including Ni and a plurality of ceramic dielectric layers are alternately stacked, and external electrodes. The ceramic dielectric layer includes an inner dielectric layer located between internal electrodes, and an outer dielectric layer located outside in a stacking direction and including at least NiO. A difference between average grain sizes of dielectric grains of the outer dielectric layers and the inner dielectric layers is about 10% or less. A molar amount of NiO with respect to about 100 moles of Ti is larger by about 0.6 mole or more in the outer dielectric layer than in the inner dielectric layer.

Claims (30)

1. A multilayer ceramic capacitor comprising:

a multilayer body including a plurality of internal electrodes and a plurality of ceramic dielectric layers that are alternately stacked; and

a plurality of external electrodes provided on surfaces of the multilayer body and electrically connected to the plurality of internal electrodes; wherein

the multilayer body includes a first main surface and a second main surface that oppose each other in a stacking direction, a first side surface and a second side surface that oppose each other in a width direction orthogonal or substantially orthogonal to the stacking direction, and a first end surface and a second end surface that oppose each other in a length direction orthogonal or substantially orthogonal to the stacking direction and the width direction;

the plurality of internal electrodes include Ni;

the plurality of ceramic dielectric layers include:

an outer dielectric layer located further outside, in the stacking direction, than an outermost one of the plurality of internal electrodes in the stacking direction; and

an inner dielectric layer located between two of the plurality of internal electrodes adjacent to each other in the stacking direction;

the outer dielectric layer includes at least Ti and NiO;

the inner dielectric layer includes at least Ti;

an average grain size of dielectric grains included in the plurality of ceramic dielectric layers is about 180 nm or more and about 220 nm or less;

when a ratio of a difference between an average grain size D 1 of dielectric grains included in the inner dielectric layer and an average grain size D 2 of dielectric grains included in the outer dielectric layer with respect to the average grain size D 1 of dielectric grains included in the inner dielectric layer is defined, the ratio satisfies the equation (D 2 −D 1 )/D 1 ≤0.1;

a thickness of the inner dielectric layer is about 4 μm or more, a thickness of the outer dielectric layer is about 100 μm or more and about 200 μm or less, and thicknesses of the inner electrodes are about 1 μm or more; and

a molar amount of NiO with respect to 100 moles of Ti included in the outer dielectric layer is larger by about 0.6 mole or more than a molar amount of NiO with respect to 100 moles of Ti included in the inner dielectric layer.

2. The multilayer ceramic capacitor according to claim 1 , wherein

a dimension in the length direction of the multilayer body is about 1.2 mm or more;

a dimension in the width direction of the multilayer body is about 0.6 mm or more; and

a dimension in the stacking direction of the multilayer body is about 0.6 mm or more.

3. The multilayer ceramic capacitor according to claim 1 , wherein when a ratio of a difference between continuity K 1 of an internal electrode located in a central portion in the stacking direction and continuity K 2 of the outermost one of the plurality of internal electrodes in the stacking direction with respect to the continuity K 1 of the internal electrode located in the central portion in the stacking direction is defined, the ratio is expressed as (K 1 −K 2 )/K 1 ≤0.1.

4. The multilayer ceramic capacitor according to claim 1 , wherein at least one corner or ridge of the multilayer body is rounded.

5. The multilayer ceramic capacitor according to claim 1 , wherein the plurality of ceramic dielectric layers include dielectric grains of a perovskite structure.

6. The multilayer ceramic capacitor according to claim 1 , wherein the plurality of internal electrodes include first internal electrodes that extend to the first end surface of the multilayer body and second internal electrodes that extend to the second end surface of the multilayer body.

7. The multilayer ceramic capacitor according to claim 6 , wherein

the first internal electrodes each include a first counter electrode portion that opposes the second internal electrodes, and a first extended electrode portion that extends from the first counter electrode portion to the first end surface of the multilayer body; and

the second internal electrodes each include a second counter electrode portion that opposes the first internal electrodes, and a second extended electrode portion that extends from the second counter electrode portion to the second end surface of the multilayer body.

8. The multilayer ceramic capacitor according to claim 7 , wherein the first counter electrode portion and the second counter electrode portion oppose each other with the inner dielectric layer located therebetween to provide a capacitance.

9. The multilayer ceramic capacitor according to claim 6 , wherein

the plurality of external electrodes include a first external electrode provided on the first end surface of the multilayer body and a second external electrode provided on a second end surface of the multilayer body;

the first external electrode is electrically connected to the first internal electrodes; and

the second external electrode is electrically connected to the second internal electrodes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2019
From: YAO, YUICHIRO; FUKUMURA, KEISUKE
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 050730/0313 →
Priority Claims (1)
JP JP2018-198243 · Oct 22, 2018 · national
Continuity (1)
Related Publication 20200126731A1 · Apr 23, 2020