RRAM structure with only part of variable resistive layer covering bottom electrode and method of fabricating the same

1. An RRAM structure comprising:

a substrate divided into a memory cell region and a logic device region;

a metal plug disposed within the memory cell region;

an RRAM disposed on and contacts the metal plug, wherein the RRAM comprises a top electrode, a variable resistive layer, and a bottom electrode, the variable resistive layer is disposed between the top electrode and the bottom electrode, the variable resistive layer comprises a first bottom surface, the bottom electrode comprises a first top surface, the first bottom surface and the first top surface are coplanar and only part of the first bottom surface overlaps and contacts the first top surface, and a fifth width of the variable resistive layer, a sixth width of the top electrode and a fourth width of the bottom electrode are the same, and the fourth width, the fifth width and the sixth width are parallel to a top surface of the substrate.

2. The RRAM structure of claim 1 , wherein the top electrode has a second bottom surface, the variable resistive layer has a second top surface, the second bottom surface contacts and entirely overlaps the second top surface.

3. The RRAM structure of claim 1 , wherein the first top surface has a first width, the first bottom surface has a second width, the first width equals to the second width, the first width is parallel to the second width, the first width only partly overlaps the second width and wherein 50% to 95% of the first width overlaps the second width.

4. The RRAM structure of claim 1 , further comprising:

a third metal dielectric covering the memory cell region and the logic device region, wherein the metal plug penetrates the third metal dielectric within the memory cell region;

a fourth metal dielectric covering the third metal dielectric, the memory cell region and the logic device region, wherein the RRAM is embedded in the fourth metal dielectric;

a second plug disposed in the third metal dielectric within the logic device region;

a third metal layer covering and contacting the second plug, wherein the third metal layer is disposed in the third metal dielectric;

a third plug disposed in the fourth metal dielectric within the logic device region;

a fourth metal layer covering and contacting the third plug, wherein the fourth metal layer is disposed in the fourth metal dielectric; and

a fourth drain metal layer covering and contacting the top electrode of the RRAM.

5. The RRAM structure of claim 4 , wherein a summation of a height of the second plug and a height of the third metal layer equals to a height of the metal plug.

6. The RRAM structure of claim 4 , wherein a summation of a height of the third plug and a height of the fourth metal layer equals to a summation of a height of the RRAM and a height of the fourth drain metal layer.

7. The RRAM structure of claim 4 , further comprising a first transistor disposed within the logic device region of the substrate, wherein the first transistor electrically connects the second plug, the third metal layer, the third plug and the fourth metal layer.

8. The RRAM structure of claim 4 , wherein a summation of a height of the RRAM and a height of the fourth drain metal layer equals to a height of the metal plug.

9. The RRAM structure of claim 1 , further comprising a second transistor disposed in the memory cell region of the substrate, wherein a drain of the second transistor electrically connects to the metal plug and the RRAM.

10. The RRAM structure of claim 1 , wherein the first bottom surface is parallel to a top surface of the substrate.