Sonos stack with split nitride memory layer
A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.
1. A non-volatile memory device comprising:
a channel region formed from a semiconductor material;
a tunnel dielectric layer abutting the channel region;
a charge-trapping layer stack abutting the tunnel dielectric layer, the charge-trapping layer stack comprising at least a first nitride layer proximate to the tunnel dielectric layer and a second nitride layer away from the tunnel dielectric layer;
a blocking dielectric layer abutting the charge-trapping layer stack; and
a gate layer abutting the blocking dielectric layer,
wherein the first and second nitride layers comprise oxynitride and the first nitride layer is oxygen rich relative to the second nitride layer.
2. The non-volatile memory device of claim 1 , wherein the tunnel dielectric layer is a tunnel oxide layer.
3. The non-volatile memory device of claim 1 , wherein the semiconductor material is polysilicon.
4. The non-volatile memory device of claim 1 , wherein the gate layer is metal.
5. The non-volatile memory device of claim 1 , wherein the gate layer is polysilicon.
6. The non-volatile memory device of claim 1 , wherein the semiconductor material is selected from the group consisting of silicon, germanium, silicon-germanium, gallium-arsenide, germanium, gallium-nitride and aluminum-phosphide.
7. The non-volatile memory device of claim 1 , wherein the charge-trapping layer stack further comprises an intermediate oxide layer interposed between the first nitride layer and the second nitride layer.
8. The non-volatile memory device of claim 7 , wherein the intermediate oxide layer comprises a thickness of at least 5 Å.
9. The non-volatile memory device of claim 1 , wherein the first and second nitride layers each comprise a thickness of at least 30 Å.
10. The non-volatile memory device of claim 9 , wherein the first nitride layer comprises a thickness in a range of 30 Å to 80 Å.
11. The non-volatile memory device of claim 1 , wherein the blocking dielectric layer is a blocking oxide layer.
12. The non-volatile memory device of claim 11 , wherein the blocking oxide layer comprises a thickness in a range of 30 Å to 70 Å.
13. The non-volatile memory device of claim 12 , wherein the blocking oxide layer comprises a thickness in a range of 40 Å to 50 Å.