Stacked transistors
A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.
1. An electronic device comprising:
a first transistor layer on a second transistor layer;
a first interconnect layer coupled to a first source/drain region on the first transistor layer;
a first gate on the first transistor layer, the first gate having a first composition, wherein the first gate is an N-type gate;
a second interconnect layer coupled to a second source/drain region on the second transistor layer, the second interconnect layer having an uppermost surface; and
a second gate on the second transistor layer, the second gate having a second composition different than the first composition, wherein the second gate is a P-type gate, and wherein the second gate is directly on the first gate, and wherein the second gate has a bottommost surface above the uppermost surface of the second interconnect layer.
2. The electronic device of claim 1 , wherein a portion of the first interconnect layer is extended through the first source/drain region coupled to the second source/drain region.
3. The electronic device of claim 1 , wherein a portion of the first interconnect layer wraps around the first source/drain region coupled to the second source/drain region.
4. The electronic device of claim 1 , further comprising
an insulating layer underneath the first gate.
5. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first transistor layer on a second transistor layer;
a first interconnect layer coupled to a first source/drain region on the first transistor layer;
a first gate on the first transistor layer, the first gate having a first composition, wherein the first gate is an N-type gate;
a second interconnect layer coupled to a second source/drain region on the second transistor layer, the second interconnect layer having an uppermost surface; and
a second gate on the second transistor layer, the second gate having a second composition different than the first composition, wherein the second gate is a P-type gate, and wherein the second gate is directly on the first gate, and wherein the second gate has a bottommost surface above the uppermost surface of the second interconnect layer.
6. The computing device of claim 5 , further comprising:
a memory coupled to the board.
7. The computing device of claim 5 , further comprising:
a communication chip coupled to the board.
8. The computing device of claim 5 , further comprising:
a camera coupled to the board.
9. The computing device of claim 5 , further comprising:
a battery coupled to the board.
10. The computing device of claim 5 , further comprising:
an antenna coupled to the board.
11. The computing device of claim 5 , wherein the component is a packaged integrated circuit die.
12. The computing device of claim 5 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
13. The computing device of claim 5 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.
14. The computing device of claim 5 , wherein a portion of the first interconnect layer is extended through the first source/drain region coupled to the second source/drain region.
15. The computing device of claim 5 , wherein a portion of the first interconnect layer wraps around the first source/drain region coupled to the second source/drain region.
16. The computing device of claim 5 , further comprising an insulating layer underneath the first gate.
17. An electronic device comprising:
a first transistor layer on a second transistor layer;
a first interconnect layer coupled to a first source/drain region on the first transistor layer;
a first gate on the first transistor layer;
a second interconnect layer coupled to a second source/drain region on the second transistor layer, the second interconnect layer having an uppermost surface; and
a second gate on the second transistor layer, the second gate having a material layer not included in the first gate, wherein the second gate is directly on the first gate, and wherein the second gate has a bottommost surface above the uppermost surface of the second interconnect layer.
18. An electronic device comprising:
a first transistor layer on a second transistor layer;
a first interconnect layer coupled to a first source/drain region on the first transistor layer;
a first gate on the first transistor layer, the first gate having a first composition;
a second interconnect layer coupled to a second source/drain region on the second transistor layer, the second interconnect layer having an uppermost surface; and
a second gate on the second transistor layer, the second gate having a second composition, an entirety of the second composition different than an entirety of the first composition, wherein the second gate is directly on the first gate, and wherein the second gate has a bottommost surface above the uppermost surface of the second interconnect layer.
19. An electronic device comprising:
a first transistor layer on a second transistor layer;
a first interconnect layer coupled to a first source/drain region on the first transistor layer;
a first gate on the first transistor layer;
a second interconnect layer coupled to a second source/drain region on the second transistor layer, the second interconnect layer having an uppermost surface; and
a second gate on the second transistor layer, wherein the second gate is directly on the first gate, and wherein the second gate meets the first gate at a physical interface, and wherein the second gate has a bottommost surface above the uppermost surface of the second interconnect layer.