Analog-digital converter

1. An analog-to-digital converter comprising:

a track-and-hold circuit configured to sample and hold an analog input voltage and output a held voltage obtained by sampling and holding the analog input voltage;

a first comparison circuit including n 2 K +2 voltage comparators (where K is an integer of at least 1 and less than N (where N is an integer of at least 2) and n is an integer of 0 to 2 K +1), the first comparison circuit being configured to compare, at each of the voltage comparators, reference voltages respectively assigned to the voltage comparators with the held voltage to output 2 K +2 voltage comparison results;

a latch circuit configured to latch the voltage comparison results to generate a thermometer code indicating x target approximate voltage ranges (where x is an integer of 1 to 2 K ) including the held voltage among 2 K preset approximate voltage ranges;

a second comparison circuit including m 2 K time comparison circuits (where m is an integer of 1 to 2 K ) corresponding to the target approximate voltage ranges, respectively, the second comparison circuit being configured such that a target time comparison circuit corresponding to the target approximate voltage range among the time comparison circuits is configured to compare a comparison operation time difference included in voltage comparison results, among the voltage comparison results output from the first comparison circuit, regarding two adjacent approximate voltage ranges that are vertically adjacent to the target approximate voltage range with 2 L reference times (where L=N−K) corresponding to 2 L specific voltage ranges and generate a target binary code of L bits indicating a target specific voltage range including the held voltage within the target approximate voltage range from 2 L obtained time comparison results to output full binary codes of L×2 K bits that combine non-target binary codes of L bits output from 2 K −1 time comparison circuits other than the target time comparison circuit and the target binary code; and

an output circuit configured to generate upper K-bit binary data of a converted digital output of N bits based on the thermometer code output from the latch circuit and generate lower L-bit binary data of the converted digital output based on the full binary codes output from the second comparison circuit.

2. The analog-to-digital converter according to claim 1 , wherein the first comparison circuit is configured to compare, at each of the voltage comparators, the reference voltages assigned to the voltage comparators with the held voltage to output a positive-side output indicating that the held voltage is greater than the reference voltage and a negative-side output indicating that the held voltage is less than the reference voltage as the voltage comparison results.

3. The analog-to-digital converter according to claim 2 , wherein the latch circuit includes n 2 K +2 latches configured to perform latch operations based on the positive-side output and the negative-side output to generate the thermometer code of 2 K +2 bits based on obtained latch outputs.

4. The analog-to-digital converter according to claim 2 , wherein each of the time comparison circuits includes i 2 L time comparators (where i is an integer of 1 to 2 L ) and is configured such that, when a first time comparison circuit among the time comparison circuits is the target time comparison circuit, the first time comparison circuit compares, at the time comparators, a comparison operation time difference which is a time difference between a positive-side output of a first voltage comparator among the voltage comparators and a negative-side output of a second voltage comparator among the voltage comparators with reference times assigned to the time comparators, respectively, to generate the target binary code of L bits.

5. The analog-to-digital converter according to claim 4 , wherein each of the time comparators includes a delay circuit configured to delay one of the positive-side output and the negative-side output that are input by a first reference time among the reference times and a latch circuit configured to perform a latch operation based on the positive-side output and the negative-side output output from the delay circuit to output 1-bit binary data indicating a time comparison result between the comparison operation time difference and the first reference time.

6. The analog-to-digital converter according to claim 4 , wherein each of the time comparison circuits includes a switching circuit configured to perform switching control of an input of the negative-side output to a first time comparator among the time comparators based on the positive-side output of the first voltage comparator while performing switching control of an input of the positive-side output to the first time comparator based on the negative-side output of the second voltage comparator.

7. A method of operating an analog-to-digital converter, the method comprising:

sampling and holding, by a track-and-hold circuit, an analog input voltage, and outputting a held voltage obtained by sampling and holding the analog input voltage;

comparing, by a first comparison circuit including n 2 K +2 voltage comparators (where K is an integer of at least 1 and less than N (where N is an integer of at least 2) and n is an integer of 0 to 2 K +1), at each of the voltage comparators, reference voltages respectively assigned to the voltage comparators with the held voltage to output 2 K +2 voltage comparison results;

latching, by a latch circuit, the voltage comparison results to generate a thermometer code indicating x target approximate voltage ranges (where x is an integer of 1 to 2 K ) including the held voltage among 2 K preset approximate voltage ranges;

comparing, by a target time comparison circuit of a second comparison circuit including m 2 K time comparison circuits (where m is an integer of 1 to 2 K ) corresponding to the target approximate voltage ranges, respectively, the time target comparison circuit corresponding to the target approximate voltage range among the time comparison circuits, a comparison operation time difference included in voltage comparison results, among the voltage comparison results output from the first comparison circuit, regarding two adjacent approximate voltage ranges that are vertically adjacent to the target approximate voltage range with 2 L reference times (where L=N−K) corresponding to 2 L specific voltage ranges and generating a target binary code of L bits indicating a target specific voltage range including the held voltage within the target approximate voltage range from 2 L obtained time comparison results to output full binary codes of L×2 K bits that combine non-target binary codes of L bits output from 2 K −1 time comparison circuits other than the target time comparison circuit and the target binary code; and

generating, by an output circuit, upper K-bit binary data of a converted digital output of N bits based on the thermometer code output from the latch circuit and generating lower L-bit binary data of the converted digital output based on the full binary codes output from the second comparison circuit.

8. The method according to claim 7 , wherein the first comparison circuit compares, at each of the voltage comparators, the reference voltages assigned to the voltage comparators with the held voltage to output a positive-side output indicating that the held voltage is greater than the reference voltage and a negative-side output indicating that the held voltage is less than the reference voltage as the voltage comparison results.

9. The method according to claim 8 , wherein the latch circuit includes n 2 K +2 latches performing latch operations based on the positive-side output and the negative-side output to generate the thermometer code of 2 K +2 bits based on obtained latch outputs.

10. The method according to claim 8 , wherein each of the time comparison circuits includes i 2 L time comparators (where i is an integer of 1 to 2 L ), and wherein, when a first time comparison circuit among the time comparison circuits is the target time comparison circuit, the first time comparison circuit compares, at the time comparators, a comparison operation time difference which is a time difference between a positive-side output of a first voltage comparator among the voltage comparators and a negative-side output of a second voltage comparator among the voltage comparators with reference times assigned to the time comparators, respectively, to generate the target binary code of L bits.

11. The method according to claim 10 , wherein each of the time comparators includes a delay circuit delaying one of the positive-side output and the negative-side output that are input by a first reference time among the reference times and a latch circuit performing a latch operation based on the positive-side output and the negative-side output output from the delay circuit to output i-bit binary data indicating a time comparison result between the comparison operation time difference and the first reference time.

12. The method according to claim 10 , wherein each of the time comparison circuits includes a switching circuit performing switching control of an input of the negative-side output to a first time comparator among the time comparators based on the positive-side output of the first voltage comparator while performing switching control of an input of the positive-side output to the first time comparator based on the negative-side output of the second voltage comparator.