Addition method, semiconductor device, and electronic device
An adder circuit inhibiting overflow is provided. A first memory, a second memory, a third memory, and a fourth memory are included. A step of supplying first data with a sign to the first memory and supplying the first data with a positive sign stored in the first memory, to the second memory; a step of supplying the first data with a negative sign stored in the second memory, to the third memory; a step of generating second data by adding the first data with a positive sign stored in the second memory and the first data with a negative sign stored in the third memory; and a step of storing the second data in the fourth memory are included. When the second data stored in the fourth memory are all second data with a positive sign or all second data with a negative sign, all the second data stored in the fourth memory are added.
1. A semiconductor device comprising a neural network,
wherein the neural network comprises a product-sum operation circuit,
wherein the product-sum operation circuit comprises a plurality of multiplier circuits and a first circuit,
wherein the first circuit comprises a first memory, a second memory, a third memory, and a first adder circuit,
wherein output data of the multiplier circuits are supplied to the first memory as first data with a positive sign and second data with a negative sign,
wherein the first data with the positive sign is supplied to the second memory,
wherein the second data with the negative sign is supplied to the third memory, and
wherein the first adder circuit is configured to add the first data with the positive sign and the second data with the negative sign.
2. The semiconductor device according to claim 1 ,
wherein the second memory and the third memory have a first-in-first-out function.
3. An electronic device comprising:
the semiconductor device according to claim 1 ; and
a housing in which the semiconductor device is placed.