IP Library Granted Patent US 11,263,141
Granted Patent B2
US 11,263,141 · App. 17/026,264 · Granted Mar 1, 2022

Sector cache for compression

Inventors: Abhishek R. Appu (El Dorado Hills, CA); Altug Koker (El Dorado Hills, CA); Joydeep Ray (Folsom, CA); David Puffer (Tempe, AZ); Prasoonkumar Surti (Folsom, CA); Lakshminarayanan Striramassarma (El Dorado Hills, CA); Vasanth Ranganathan (El Dorado Hills, CA); Kiran C. Veernapu (Bangalore, IN); Balaji Vembu (Folsom, CA); Pattabhiraman K (Bangalore, IN)
Assignee: INTEL CORPORATION
G06F12/0877G06F12/0802G06F12/0806G06F12/0848G06F12/0855G06F12/0868G06F12/126G06T1/60G06F12/0893
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,263,141
App. No.
17/026,264
Granted
Mar 1, 2022
Kind
B2
Abstract

In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

Claims (46)

1. An apparatus comprising:

a shared cache memory communicatively coupled to a plurality of processing resources, the shared cache memory structured into a plurality of sectors, at least one sector in the plurality of sectors comprising at least a first cache line and a second cache line; and

a processing unit to:

implement victim selection during a cache eviction from the shared cache memory, receive a cache access request to the shared cache memory, the cache access request comprising a pairing bit field; and

use the pairing bit field to locate the at least a first cache line and a second cache line associated with the cache access request to the shared cache memory,

wherein the victim selection is to assign:

a high priority to a cache sector which includes at least one invalid cache line;

a medium priority to a cache sector in which neither the first cache line nor the second cache line are identified as a victim; and

a low priority to a cache sector in the first cache line and the second cache line are valid.

2. The apparatus of claim 1 , further comprising:

a data compression unit communicatively coupled to the cache memory, wherein the data compression unit operates at a sector-level granularity.

3. The apparatus of claim 1 , wherein the general-purpose graphics processing compute block includes multiple compute clusters, each compute cluster including multiple graphics multiprocessors.

4. The apparatus of claim 1 , wherein the victim selection algorithm is to assign a high priority to cache sectors which are invalid.

5. The apparatus of claim 1 , wherein the victim selection algorithm is to assign a high priority to cache sectors which are valid and include at least one invalid cacheline.

6. The apparatus of claim 1 , wherein the victim selection algorithm is to assign a low priority to cache sectors which are valid and include at least all invalid cachelines.

7. A method comprising:

structuring a shared cache memory communicatively coupled to the plurality of processing resources of a general purpose graphics compute block into plurality of sectors, at least one sector in the plurality of sectors comprising at least a first cache line and a second cache line;

receiving, in a processing unit, a cache access request to the shared cache memory, the cache access request comprising a pairing bit field; and

using, in the processing unit, the pairing bit field to locate the at least a first cache line and a second cache line associated with the cache access request to the shared cache memory; and

implementing victim selection during a cache eviction from the shared cache memory, wherein the victim selection is to assign:

a high priority to a cache sector which includes at least one invalid cache line;

a medium priority to a cache sector in which neither the first cache line nor the second cache line are identified as a victim; and

a low priority to a cache sector in the first cache line and the second cache line are valid.

8. The method of claim 7 , further comprising:

compressing the data in the shared cache memory at a sector-level granularity.

9. The method of claim 8 , further comprising implementing a process to assign the one or more extra threads to one or more streaming multiprocessors which are assigned to a different context.

10. The method of claim 9 , wherein the general-purpose graphics processing compute block includes multiple compute clusters, each compute cluster including multiple graphics multiprocessors.

11. The method of claim 7 , wherein the victim selection algorithm is to assign a high priority to cache sectors which are invalid.

12. The method of claim 7 , wherein the victim selection algorithm is to assign a high priority to cache sectors which are valid and include at least one invalid cacheline.

13. The method of claim 7 , wherein the victim selection algorithm is to assign a low priority to cache sectors which are valid and include at least all invalid cachelines.

14. One or more non-transitory computer-readable medium comprising one or more instructions that when executed on a processing unit of a general purpose graphics processing, configure the processing unit to perform one or more operations comprising:

structuring a shared cache memory communicatively coupled to the plurality of processing resources of a general purpose graphics compute block into plurality of sectors, at least one sector in the plurality of sectors comprising at least a first cache line and a second cache line;

receiving, in a processing unit, a cache access request to the shared cache memory, the cache access request comprising a pairing bit field; and

using, in the processing unit, the pairing bit field to locate the at least a first cache line and a second cache line associated with the cache access request to the shared cache memory; and

implementing victim selection during a cache eviction from the shared cache memory, wherein the victim selection is to assign:

a high priority to a cache sector which includes at least one invalid cache line;

a medium priority to a cache sector in which neither the first cache line nor the second cache line are identified as a victim; and

a low priority to a cache sector in the first cache line and the second cache line are valid.

15. The one or more non-transitory computer-readable medium of claim 14 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:

compress the data in the shared cache memory at a sector-level granularity.

16. The one or more non-transitory computer-readable medium of claim 14 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:

implement a process to assign the one or more extra threads to one or more streaming multiprocessors which are assigned to a different context.

17. The one or more non-transitory computer-readable medium of claim 14 , wherein the general-purpose graphics processing compute block includes multiple compute clusters, each compute cluster including multiple graphics multiprocessors.

18. The one or more non-transitory computer-readable medium of claim 14 , wherein the victim selection algorithm is to assign a high priority to cache sectors which are invalid.

19. The one or more non-transitory computer-readable medium of claim 14 , wherein the victim selection algorithm is to assign a high priority to cache sectors which are valid and include at least one invalid cacheline.

20. The one or more non-transitory computer-readable medium of claim 14 , wherein the victim selection algorithm is to assign a low priority to cache sectors which are valid and include at least all invalid cachelines.

Continuity (3)
Continuation 16702073 · Dec 3, 2019
Continuation 15477058 · Apr 1, 2017
Related Publication 20210056033A1 · Feb 25, 2021
Cited By (1)
US 12,430,264