Multi-row standard cell design method in hybrid row height system
View Patent ↗A discrete multi-row height cell in a hybrid row-height system with a plurality of rows of at least two different row-heights is disclosed. The discrete multi-row height cell includes: a first sub-cell deployed on a first row with a first row-height; a second sub-cell deployed on a second row with a second row-height, wherein the second row and the first row is separated by a third row with a third row-height, wherein the third row-height is different from the first row-height, wherein the first sub-cell and the second sub-cell are electrically connected by at least a wire.
1. An integrated circuit (IC) layout, the IC layout comprising:
a plurality of rows of at least two different row-heights;
a discrete multi-row cell deployed over the plurality of rows, the multi-row cell comprising:
a first sub-cell deployed on at least a first row of cells with a first row-height;
a second sub-cell deployed on at least a second row of cells with a second row-height, and
empty spaces surrounding the first and second sub-cells,
wherein the first row and the second row have different number of fins corresponding to at least two different row-heights,
wherein the empty spaces are used for filling in other cells of matching geometry,
wherein the multi-row cell comprises a sub-cell covering more than one row,
wherein the second row of cells and the first row of cells are separated by a third row of cells with a third row-height,
wherein the third row-height is different from the first row-height, and
wherein the first sub-cell and the second sub-cell are electrically connected by at least a wire in the empty spaces.
2. The IC layout of claim 1 , wherein the third row-height is different from the second row-height.
3. The IC layout of claim 1 , wherein the first row-height and the second row-height are the same.
4. The IC layout of claim 1 , wherein the first row-height and the second row-height are different.
5. The IC layout of claim 1 , wherein the third row-height is smaller than the first row-height.
6. The IC layout of claim 1 , wherein the third row-height is smaller than both the first row-height and the second row-height.
7. The IC layout of claim 1 , wherein the first sub-cell is of the same size as the second sub-cell.
8. The IC layout of claim 1 , wherein the first sub-cell is of a size different from the second sub-cell.
9. A method for IC layout design, the method comprising:
obtaining hybrid-row specifications with different row heights;
obtaining cell driving target specifications;
analyzing hybrid-row specifications with different row heights;
deriving discrete multi-row cell styles;
generating the discrete multi-row cell by splitting a cell into discrete sub-cells with matching geometry and target cell driving specifications;
conducting the discrete multi-row cell quality control to ensure the generated discrete multi-row cell match quality control targets; and
under a condition if the quality control fails, re-generating the discrete multi-row cell by splitting the cell into sub-cells with matching geometry and target cell driving specifications.
10. The method of claim 9 , further comprises:
under a condition if the quality control passes, generating a marker layer of empty spaces to potentially accommodate other cells in the empty space with matching geometry and performance specifications.
11. The method of claim 9 , further comprises:
completing the generation of discrete multi-row cell with matching specifications.
12. The method of claim 9 , wherein analyzing hybrid-row specifications further comprises:
decomposing a hybrid-row system to understand the specification of each row style.
13. The method of claim 12 , wherein analyzing hybrid-row specifications further comprises:
estimating an achievable driving strength of the discrete multi-row cell according to the hybrid-row specification and the cell driving target specifications.
14. The method of claim 9 , wherein deriving discrete multi-row cell styles further comprises:
generating available discrete multi-row styles and compositions.
15. The method of claim 9 , wherein conducting discrete multi-row cell quality control further comprises:
analyzing the generated discrete multi-row cell to ensure no design rule violation in the generated discrete multi-row cell and among other cells.
16. The method of claim 10 , wherein generating a marker layer of the empty spaces further comprises:
implementing the marker layer of the empty spaces to allow wire feed through.
17. The method of claim 10 , wherein generating a marker layer of the empty spaces further comprises:
implementing the marker layer of the empty spaces to allow other cell placement.
18. The method of claim 10 , wherein generating a marker layer on the empty spaces is implemented to achieve better area shrinking ratio and to reduce the impact of discrete multi-row cells.
19. An IC layout designed by a process, the process comprising:
obtaining hybrid-row specifications with different row heights;
obtaining cell driving target specifications;
analyzing the hybrid-row specifications with different row heights;
deriving discrete multi-row cell styles;
generating the discrete multi-row cell by splitting a cell into discrete sub-cells with matching geometry and target cell driving specifications;
conducting the discrete multi-row cell quality control to ensure the generated discrete multi-row cell match quality control targets; and
under a condition if the quality control fails, re-generating the discrete multi-row cell by splitting the cell into sub-cells with matching geometry and target cell driving specifications.
20. The IC layout of claim 19 , wherein the process further comprises:
under a condition if the quality control passes, generating a marker layer of empty spaces to potentially accommodate other cells in the empty space with matching geometry and performance specifications.