Method of programming in flash memory devices
A memory device includes a plurality of memory cells. Each row of the plurality of memory cells is coupled to a respective one of a plurality of wordlines. A method of programming the memory device includes applying a program voltage to a selected wordline of the plurality of wordlines. The method also includes applying a series of incremental verifying voltages to the selected wordline in a first time period after applying the program voltage. The method further includes floating an unselected wordline of the plurality of wordlines in a second time period at least partially overlapping the first time period. The unselected wordline is adjacent to the selected wordline.
1. A memory device, comprising:
a first memory cell;
a second memory cell;
a first word line coupled to the first memory cell and configured to:
receive a program voltage during a first time period; and
receive a verifying voltage during a second time period after the first time period; and
a second word line coupled to the second memory cell and adjacent to the first word line and, the second word line configured to receive a pre-pulse voltage during a third time period between the first and the second time periods.
2. The memory device of claim 1 , wherein the first word line is immediately and physically adjacent to the second word line.
3. The memory device of claim 1 , wherein the second word line is further configured to receive a floating voltage during a fourth time period after the third time period.
4. The memory device of claim 3 , wherein the fourth time period at least partially overlaps the second time period.
5. The memory device of claim 4 , wherein the fourth and second time periods end at a same time.
6. The memory device of claim 4 , wherein the fourth and second time periods start at a same time.
7. The memory device of claim 4 , wherein the fourth time period starts earlier than the second time period.
8. The memory device of claim 3 , wherein the second word line is further configured to receive a post-pulse voltage during a fifth time period after the fourth time period.
9. The memory device of claim 1 , further comprising:
a third memory cell; and
a third word line coupled to the third memory cell and configured to receive a pass voltage during the second time period.
10. The memory device of claim 9 , wherein the third word line is immediately and physically adjacent to the second word line.
11. A memory device, comprising:
a first memory cell;
a second memory cell;
a first word line coupled to the first memory cell;
a second word line coupled to the second memory cell and adjacent to the first word line; and
a control circuit coupled to the first and second word lines and configured to:
apply a program voltage on the first word line during a first time period;
apply a verifying voltage on the first word line during a second time period after the first time period; and
apply a pre-pulse voltage on the second word line during a third time period between the first and the second time periods.
12. The memory device of claim 11 , wherein the first word line is immediately and physically adjacent to the second word line.
13. The memory device of claim 11 , wherein the control circuit is further configured to apply a floating voltage on the second word line during a fourth time period after the third time period.
14. The memory device of claim 13 , wherein the fourth time period at least partially overlaps the second time period.
15. The memory device of claim 14 , wherein the fourth and second time periods end at a same time.
16. The memory device of claim 14 , wherein the fourth and second time periods start at a same time.
17. The memory device of claim 14 , wherein the fourth time period starts earlier than the second time period.
18. A memory device, comprising:
a first memory cell;
a second memory cell;
a first word line coupled to the first memory cell and configured to receive a verifying voltage during a first time period; and
a second word line coupled to the second memory cell,
wherein the second word line is configured to receive a voltage to offset a parasitic voltage caused by a parasitic capacitance between the first and second word lines during the first time period.
19. The memory device of claim 18 , wherein the first word line is immediately and physically adjacent to the second word line.
20. The memory device of claim 18 , wherein the second word line is configured to receive a floating voltage during a second time period at least partially overlapping the first time period.