Reduced-leakage apparatus for sampling electrical signals and associated methods

1. An apparatus, comprising:

a sample-and-hold (S/H) circuit, comprising:

a first switch coupled to provide an input signal to be sampled;

a second switch coupled to the first switch and to a first capacitor, wherein a gate of the second switch is coupled to a buffer, and wherein the buffer is coupled to a supply voltage provided by a native transistor;

a third switch to provide the input signal to a second capacitor; and

a fourth switch to selectively couple to ground a node between the first and second switches.

2. The apparatus according to claim 1 , wherein the fourth switch is closed during a hold mode of the S/H circuit.

3. The apparatus according to claim 2 , wherein the fourth switch is open during a sample mode of the S/H circuit.

4. The apparatus according to claim 1 , wherein the first, second, third, and fourth switches comprise, respectively, first, second, third, and fourth metal semiconductor field effect transistors (MOSFETs).

5. The apparatus according to claim 1 , wherein a bulk of the second switch is coupled to a source of a native transistor, and wherein a drain of the second switch is coupled to a gate of the native transistor.

6. The apparatus according to claim 1 , further comprising a diode coupled to the second switch and to a source of a native transistor, wherein a gate of the native transistor is coupled to the second switch.

7. A method of using a sample and hold (S/H) circuit having a sample mode and a hold mode, the method comprising:

providing, by using a first switch, an input signal to be sampled;

using a second switch to provide the input signal to a first capacitor;

supplying a gate voltage of the second switch by using a buffer;

supplying power to the buffer by using a native transistor;

using a third switch to provide the input signal to a second capacitor; and

selectively coupling, by using a fourth switch, to ground a node between the first and second switches.

8. The method according to claim 7 , wherein selectively coupling, by using the fourth switch, to ground the node between the first and second switches further comprises closing the fourth switch during the hold mode of the S/H circuit.

9. The method according to claim 7 , wherein selectively coupling, by using the fourth switch, to ground the node between the first and second switches further comprises opening the fourth switch during the sample mode of the S/H circuit.

10. The method according to claim 7 , further comprising:

driving a bulk of the second switch by a source of a native transistor; and

driving a gate of the native transistor by a drain of the second switch.

11. The method according to claim 7 , further comprising driving, by using a native transistor, a diode coupled to the second switch, wherein a gate of the native transistor is coupled to the second switch.

12. The method according to claim 7 , wherein the first, second, third, and fourth switches comprise, respectively, first, second, third, and fourth metal semiconductor field effect transistors (MOSFETs).

13. The apparatus according to claim 1 , wherein a drain of the native transistor is coupled to the supply voltage.

14. The apparatus according to claim 13 , wherein a source of the native transistor supplies power to the buffer.

15. The apparatus according to claim 5 , wherein a drain of the native transistor is coupled to a supply voltage.

16. The apparatus according to claim 6 , wherein the diode is coupled to a drain of the second switch.

17. The apparatus according to claim 16 , wherein a drain of the native transistor is coupled to ground.

18. The apparatus according to claim 6 , wherein the gate of the native transistor is coupled to a drain of the second switch.

19. The method according to claim 7 , wherein a drain of the native transistor is coupled to the supply voltage.

20. The method according to claim 7 , wherein a source of the native transistor supplies power to the buffer.