Semiconductor memory device with air gaps between conductive features and method for preparing the same

1. A semiconductor memory device, comprising:

an isolation layer defining a first active region in a substrate;

a first doped region positioned in the first active region;

a first word line buried in a first trench adjacent to the first doped region;

a high-level bit line contact positioned on the first doped region;

a first air gap surrounding the high-level bit line contact;

a second word line buried in a second trench in a second active region of the substrate, the second active region being separated from the first active region by the isolation layer;

a second doped region positioned adjacent to the second word line;

a low-level bit line positioned over the second doped region;

a second air gap positioned adjacent to the low-level bit line;

a high-level bit line positioned on the high-level bit line contact; and

a low-level bit line contact positioned between the low-level bit line and the second doped region;

wherein the first word line comprises a lower electrode structure and an upper electrode structure on the lower electrode structure;

wherein the upper electrode structure comprises: a source layer substantially covering a sidewall of the first trench; a conductive layer on the source layer; and a work-function adjustment layer disposed between the source layer and the conductive layer;

wherein a height of the low-level bit line contact is less than a height of the high-level bit line contact.

2. The semiconductor memory device of claim 1 , wherein a width of the low-level bit line is greater than a width of the low-level bit line contact.

3. The semiconductor memory device of claim 1 , wherein a width of the high-level bit line is greater than a width of the high-level bit line contact.

4. The semiconductor memory device of claim 1 , wherein a height of the high-level bit line contact is substantially the same as a combined height of the low-level bit line contact and the low-level bit line.

5. The semiconductor memory device of claim 1 , wherein a top surface of the high-level bit line contact and a top surface of the low-level bit line are substantially at the same level.

6. The semiconductor memory device of claim 1 , wherein the high-level bit line is asymmetrically positioned on the high-level bit line contact.

7. The semiconductor memory device of claim 1 , wherein a work function of the lower electrode structure is higher than a work function of the upper electrode structure.

8. The semiconductor memory device of claim 1 , wherein the work-function adjustment layer conformally covers an inner sidewall of the source layer.

9. The semiconductor memory device of claim 1 , wherein the source layer extends between the lower electrode structure and the conductive layer to cover a top surface of the lower electrode structure.

10. The semiconductor memory device of claim 1 , wherein the work-function adjustment layer includes a metal or a metal nitride, and wherein the work-function adjustment element includes lanthanum (La).

11. A method for preparing a semiconductor memory device, comprising:

forming an isolation layer defining a first active region in a substrate;

forming a first doped region in the first active region;

forming a first word line buried in a first trench adjacent to the first doped region;

forming a high-level bit line contact positioned on the first doped region;

forming a first air gap surrounding the high-level bit line contact;

wherein the forming of the first word line comprises: forming a lower electrode structure and an upper electrode structure on the lower electrode structure;

wherein the forming of the upper electrode structure comprises: forming a source layer substantially covering a sidewall of the first trench; forming a conductive layer on the source layer;

and forming a work-function adjustment layer disposed between the source layer and the conductive layer.

12. The method for preparing a semiconductor memory device of claim 11 , further comprising:

forming a second doped region in a second active region of the substrate, the second active region being separated from the first active region by the isolation layer;

forming a second word line buried in a second trench adjacent to second doped region;

forming a low-level bit line over the second doped region; and

forming a second air gap adjacent to the low-level bit line.

13. The method for preparing a semiconductor memory device of claim 12 , further comprising:

forming a high-level bit line on the high-level bit line contact; and

forming a low-level bit line contact between the low-level bit line and the second doped region;

wherein a height of the low-level bit line contact is less than a height of the high-level bit line contact.

14. The method for preparing a semiconductor memory device of claim 13 , wherein the first air gap and the second air gap are integrally formed, and the low-level bit line contact, the low-level bit line, and the high-level bit line contact are integrally formed.

15. The method for preparing a semiconductor memory device of claim 13 , wherein a top surface of the high-level bit line contact and a top surface of the low-level bit line are substantially at the same level.

16. The method for preparing a semiconductor memory device of claim 11 , wherein a work function of the lower electrode structure is higher than a work function of the upper electrode structure.

17. The method for preparing a semiconductor memory device of claim 11 , wherein the work-function adjustment layer conformally covers an inner sidewall of the source layer.

18. The method for preparing a semiconductor memory device of claim 11 , wherein the work-function adjustment layer includes a metal or a metal nitride, and wherein the work-function adjustment element includes lanthanum (La).