Leakage prevention structure and method
A semiconductor device according to the present disclosure includes an anti-punch-through (APT) region over a substrate, a plurality of channel members over the APT region, a gate structure wrapping around each of the plurality of channel members, a source/drain feature adjacent to the gate structure, and a diffusion retardation layer. The source/drain feature is spaced apart from the APT region by the diffusion retardation layer. The source/drain feature is spaced apart from each of the plurality of channel members by the diffusion retardation layer. The diffusion retardation layer is a semiconductor material.
1. A semiconductor device, comprising:
an anti-punch-through (APT) region over a substrate;
a plurality of channel members over the APT region;
a gate structure wrapping around each of the plurality of channel members;
a source/drain feature adjacent to the gate structure;
a diffusion retardation layer; and
a plurality of inner spacer features,
wherein the source/drain feature is spaced apart from the APT region by the diffusion retardation layer,
wherein the plurality of channel members are partially spaced apart from one another by the plurality of inner spacer features,
wherein the diffusion retardation layer does not merge over the plurality of inner spacer features such that the source/drain feature is in direct contact with the plurality of inner spacer features,
wherein the source/drain feature is spaced apart from each of the plurality of channel members by the diffusion retardation layer,
wherein the diffusion retardation layer comprises a semiconductor material,
wherein the source/drain feature comprises a first n-type dopant, and
wherein the diffusion retardation layer comprises a second n-type dopant different from the first n-type dopant.
2. The semiconductor device of claim 1 , wherein the APT region comprises a p-type dopant.
3. The semiconductor device of claim 1 ,
wherein the source/drain feature comprises phosphorus (P),
wherein the APT region comprises boron (B), and
wherein the diffusion retardation layer comprises arsenide (As).
4. The semiconductor device of claim 3 ,
wherein the diffusion retardation layer comprises silicon and arsenide, and
wherein a concentration of arsenide in the diffusion retardation layer is between about 1×10 20 atoms/cm 3 and about 1×10 21 atoms/cm 3 .
5. The semiconductor device of claim 3 , wherein a concentration of boron in the APT region is between about 1×10 18 atoms/cm 3 and about 1×10 19 atoms/cm 3 .
6. The semiconductor device of claim 1 ,
wherein the plurality of inner spacer features are disposed between the source/drain feature and the gate structure.
7. The semiconductor device of claim 1 , wherein the diffusion retardation layer comprises a thickness between about 2 nm and about 12 nm.
8. A semiconductor device, comprising:
an anti-punch-through (APT) region over a substrate;
a plurality of nanostructures over the APT region;
a gate structure wrapping around each of the plurality of nanostructures;
a source/drain feature adjacent to the gate structure, the source/drain feature comprising:
an outer epitaxial feature in contact with sidewalls of the plurality of nanostructures, and
an inner epitaxial feature spaced apart from the plurality of nanostructures by the outer epitaxial feature; and
a plurality of inner spacer features interleaving the plurality of nanostructures,
wherein the outer epitaxial feature does not merge over the plurality of inner spacer features such that the source/drain feature is in direct contact with the plurality of inner spacer features, and
wherein the outer epitaxial feature comprises a first n-type dopant and the inner epitaxial feature comprises a second n-type dopant different from the first n-type dopant.
9. The semiconductor device of claim 8 ,
wherein the outer epitaxial feature is in contact with the APT region, and
wherein the outer epitaxial feature is disposed between the inner epitaxial feature and the APT region.
10. The semiconductor device of claim 8 ,
wherein the first n-type dopant is arsenide (As),
wherein the second n-type dopant is phosphorus (P), and
wherein the APT region comprises boron (B).
11. The semiconductor device of claim 10 ,
wherein the outer epitaxial feature further comprises silicon (Si), and
wherein a concentration of arsenide (As) in the outer epitaxial feature is between about 1×10 20 atoms/cm 3 and about 1×10 21 atoms/cm 3 .
12. The semiconductor device of claim 8 , further comprising:
an etch stop layer over the source/drain feature and in direct contact with the inner epitaxial feature and the outer epitaxial feature.
13. A method, comprising:
implanting a substrate with a dopant to form an anti-punch-through (APT) implant layer in the substrate;
forming a stack over the APT implant layer, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;
forming a fin-shaped active region from the stack over the APT implant layer, the fin-shaped active region comprising a channel region and a source/drain region adjacent the channel region;
forming a dummy gate stack over the channel region of the fin-shaped active region;
depositing a gate spacer layer over the dummy gate stack and the source/drain region of the fin-shaped active region;
recessing the source/drain region to form a source/drain recess;
selectively and partially recessing the plurality of sacrificial layers to form a plurality of inner spacer recesses between the plurality of channel layers;
forming a plurality of inner spacer features in the plurality of inner spacer recesses;
forming a first epitaxial layer over sidewalls of the plurality of channel layers exposed in the source/drain recess, wherein the first epitaxial layer comprises a first n-type dopant and does not merge over the plurality of inner space features; and
forming a second epitaxial layer over the first epitaxial layer, the second epitaxial layer comprising a second n-type dopant different from the first n-type dopant.
14. The method of claim 13 ,
wherein the first n-type dopant is arsenide (As), and
wherein the second n-type dopant is phosphorus (P).
15. The method of claim 14 , wherein a concentration of the first n-type dopant in the first epitaxial layer is between about 1×10 20 atoms/cm 3 and about 1×10 21 atoms/cm 3 .
16. The method of claim 13 , further comprising:
after the forming of the second epitaxial layer, annealing the first epitaxial layer and the second epitaxial layer at a temperature between about 800° C. and about 1000° C.
17. The method of claim 13 ,
wherein the forming of the fin-shaped active region comprises etching into the APT implant layer to form an APT implant region having an exposed sidewall, and
wherein the forming of the first epitaxial layer comprises epitaxially growing the first epitaxial layer from the exposed sidewall of the APT region.
18. The method of claim 13 , wherein the plurality of channel layers comprise silicon and the plurality of sacrificial layers comprise silicon germanium.
19. The method of claim 18 , wherein the forming of the plurality of inner spacer features comprises:
depositing an inner spacer material layer over the plurality of inner spacer recesses; and
etching back the deposited inner spacer material layer to expose the plurality of channel layers in the source/drain recess, so as to form the plurality of inner spacer features in the plurality of inner spacer recesses,
wherein the forming the first epitaxial layer in the source/drain recess comprises selectively and epitaxially growing the first epitaxial layer from the exposed plurality of channel layers.
20. The method of claim 19 , wherein the selectively and epitaxially growing of the first epitaxial layer from the exposed plurality of channel layers comprises epitaxially growing the first epitaxial layer until the first epitaxial layer reaches a thickness between 2 nm and about 8 nm.