IP Library › Granted Patent US 11,264,952
Granted Patent B2
US 11,264,952 · App. 17/024,245 · Granted Mar 1, 2022

Power amplification circuit

Inventors: Satoshi Tanaka (Kyoto, JP); Tetsuaki Adachi (Kyoto, JP); Kazuo Watanabe (Kyoto, JP); Masahito Numanami (Kyoto, JP); Yasuhisa Yamamoto (Kyoto, JP)
Assignee: MURATA MANUFACTURING CO., LTD.
H03F1/0205H03F1/0261H03F1/56H03F3/191H03F3/193H03F3/21H03F2200/18H03F2200/222H03F2200/387H03F2200/451H03F2200/75
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Quick Facts
Patent No.
US 11,264,952
App. No.
17/024,245
Granted
Mar 1, 2022
Kind
B2
Abstract

Provided is a power amplification circuit that includes: an amplifier that amplifies an input signal and outputs an amplified signal; a first bias circuit that supplies a first bias current or voltage to the amplifier; a second bias circuit that supplies a second bias current or voltage to the amplifier; a first control circuit that controls the first bias current or voltage; and a second control circuit that controls the second bias current or voltage. The current supplying capacity of the first bias circuit is different from the current supplying capacity of the second bias circuit.

Claims (20)

1. A power amplification circuit comprising:

an amplifier that amplifies an input signal and outputs an amplified signal;

a first bias circuit that supplies a first bias current or voltage to the amplifier;

a second bias circuit that supplies a second bias current or voltage to the amplifier;

a first control circuit that controls a level of the first bias current or voltage; and

a second control circuit that controls a level of the second bias current or voltage;

wherein a current supplying capacity of the first bias circuit is different from a current supplying capacity of the second bias circuit,

wherein the first control circuit outputs a first current that controls the first bias current or voltage,

wherein the second control circuit outputs a second current that controls the second bias current or voltage,

wherein the first bias circuit comprises a field effect transistor that outputs the first bias current or voltage in accordance with the first current,

wherein the second bias circuit comprises a second bipolar transistor that outputs the second bias current or voltage in accordance with the second current,

wherein the first bias circuit further comprises a third transistor,

wherein a collector of the third transistor is connected to a gate of the field effect transistor, a base of the third transistor is connected to a source of the field effect transistor, the emitter of the third transistor is connected to ground, and the first current is supplied to the collector of the third transistor,

wherein the second bias circuit further comprises a fourth transistor, and

wherein a collector of the fourth transistor is connected to a base of the second bipolar transistor, a base of the fourth transistor is connected to an emitter of the second bipolar transistor, an emitter of the fourth transistor is connected to ground, and the second current is supplied to the collector of the fourth transistor.

2. The power amplification circuit according to claim 1 ,

wherein the first bias circuit further comprises a first resistance element that is connected in series between the source of the field effect transistor and the amplifier,

wherein the second bias circuit further comprises a second resistance element that is connected in series between an emitter of the second bipolar transistor and the amplifier, and

wherein a resistance value of the first resistance element is different from a resistance value of the second resistance element.

3. The power amplification circuit according to claim 1 , wherein the first control circuit and the second control circuit each comprise a variable current source.

Priority Claims (1)
JP JP2016-164596 · Aug 25, 2016 · national
Continuity (3)
Division 16205904 · Nov 30, 2018
Division 15656646 · Jul 21, 2017
Related Publication 20210006205A1 · Jan 7, 2021