Symmetrically-interconnected tunable time delay circuit

1. An apparatus comprising:

a time delay circuit including

a plurality of delay units, wherein each of the plurality of delay units includes metal layers with substantially similar lengths and a same quantity of vias;

a plurality of buffer units, wherein an input of each of the plurality of buffer units is coupled to one of the plurality of delay units; wherein a quantity of the plurality of delay units equals a quantity of the plurality of buffer units; and

wherein an output of each of the plurality of buffer units is coupled to a substantially similar interconnect to drive a single metal line;

an additional delay unit coupled to a delay unit output of one of the plurality of delay units; and

a one-hot decoder coupled to each of the plurality of buffer units, the one-hot decoder configured to enable one and only one of the plurality of buffer units; and

a receive flip flop coupled to the single metal line, wherein the time delay circuit is configured to provide a tunable delay path with quasi-linear time delay.

2. The apparatus of claim 1 , wherein each of the plurality of buffer units comprises a buffer unit input and each of the plurality of delay units comprises a delay unit output.

3. The apparatus of claim 2 , wherein the buffer unit input of each of the plurality of buffer units is coupled to the delay unit output of a corresponding delay unit from the plurality of delay units.

4. The apparatus of claim 1 , wherein each of the plurality of delay units includes a time delay increment, wherein the time delay increment of each of the plurality of delay units is substantially similar.

5. The apparatus of claim 4 , wherein the quantity of the plurality of buffer units does not exceed 2N and wherein the one-hot decoder decodes a command word with N bits to enable one and only one of the plurality of buffer units, where N is an integer.

6. The apparatus of claim 1 , wherein each of the plurality of buffer units is a tri-state buffer unit.

7. A method for adaptively delaying an input signal comprising:

delaying the input signal to produce a plurality of delayed signals, wherein the delaying is implemented by a plurality of delay units each with metal layers with substantially similar lengths and a same quantity of vias;

buffering the plurality of delayed signals, wherein the buffering is implemented by a plurality of buffer units; and

enabling one of the plurality of buffer units to output one of the plurality of delayed signals to a receive flip flop, wherein each of the plurality of buffer units drives a substantially similar interconnect to a single metal line coupled to the receive flip flop.

8. The method of claim 7 , wherein each of the plurality of buffer units comprises a buffer unit input and each of the plurality of delay units comprises a delay unit output.

9. The method of claim 8 , wherein the buffer unit input of each of the plurality of buffer units is coupled to the delay unit output of a corresponding delay unit from the plurality of delay units.

10. The method of claim 7 , wherein each of the plurality of delay units includes a time delay increment, wherein the time delay increment of each of the plurality of delay units is substantially similar.

11. The method of claim 10 , wherein a quantity of the plurality of buffer units does not exceed 2N and wherein a one-hot decoder decodes a command word with N bits to enable one and only one of the plurality of buffer units, where N is an integer.

12. The method of claim 7 , further comprising adjusting a clock frequency to mitigate a supply voltage droop.

13. The method of claim 7 , wherein each of the plurality of buffer units is a tri-stat buffer unit.