Key exchange schemes with addressable elements
A computing device includes an array of addressable elements. Each addressable element is a hardware element that generates a substantially consistent response when interrogated. The device includes a processor coupled to the array of addressable elements and configured to communicate using a communication network. The processor receives a public key, and processes the public key to produce at least a set of addresses. Each address in the set of addresses identifies one or more hardware elements in the array of addressable elements. The processor generates a set of responses by interrogating the one or more hardware elements in the array of addressable elements identified by the set of addresses according to a set of reading instructions, appends the responses in the set of responses to generate a private key, receives an encrypted message and decrypts the encrypted message using the private key to generate an unencrypted message.
1. A computing device comprising:
an array of addressable elements, wherein each addressable element is a hardware element, a plurality of which generate a predictable response when interrogated;
a processor coupled to the array of addressable elements and configured to communicate using a communication network, the processor being configured to execute instructions for:
receiving, using a network interface, a public key;
processing the public key to produce at least a set of addresses, wherein each address in the set of addresses identifies one or more hardware elements in the array of addressable elements;
generating a set of responses by interrogating the one or more hardware elements in the array of addressable elements identified by the set of addresses according to a set of reading instructions;
appending the responses in the set of responses to generate a private key, at least some of the appended responses being from hardware elements having a predictable response when interrogated;
receiving, using the network interface, an encrypted message; and
decrypting the encrypted message using the private key to generate an unencrypted message.
2. The computing device of claim 1 , wherein each hardware element in the array of addressable elements is a physical unclonable function.
3. The computing device of claim 1 , wherein each address in the set of addresses identifies a series of successive hardware elements in the array of addressable elements.
4. The computing device of claim 1 , wherein processing the public key to produce at least a set of addresses additionally yields at least a set of modified reading instructions configured to modify the set of reading instructions.
5. The computing device of claim 4 , wherein processing the public key to produce at least a set of addresses additionally yields at least a set of modified reading instructions configured to modify the set of reading instructions by adjusting a spacing interval between the successive hardware elements in the array of addressable elements.
6. The computing device of claim 1 , wherein processing the public key to produce at least a set of addresses includes:
combining the public key with an additional identifying information to generate a first input;
executing a hash function on the first input to generate a hash digest; and
subdividing the hash digest into at least a set of addresses.
7. The computing device of claim 1 , wherein generating a set of responses further includes:
generating a preliminary series of responses by interrogating the hardware elements in the array of addressable elements identified by the set of addresses;
referencing the preliminary series of responses to a table of modified reading instructions; and
incorporating the modified reading instructions into subsequent reading instructions.
8. The computing device of claim 1 , wherein all of the appended responses are from addressable elements that generate a predictable response when interrogated.
9. A computing device comprising:
an array of addressable elements, wherein each addressable element is a hardware element, a plurality of which generate a predictable response when interrogated;
a processor coupled to the array of addressable elements and configured to communicate using a communication network, the processor being configured to execute instructions for:
generating, using a random number generator, a random number;
parsing the random number to produce at least a set of addresses, wherein each address in the set of addresses identifies one or more hardware elements in the array of addressable elements;
generating a set of responses by interrogating the one or more hardware elements in the array of addressable elements identified by the set of addresses according to a set of reading instructions;
appending the responses in the set of responses to generate a private key, at least some of the appended responses being from hardware elements having a predictable response when interrogated;
encrypting an unencrypted message using the private key to generate an encrypted message; and
sending, using a network interface, an encrypted message.
10. The computing device of claim 9 , wherein each hardware element in the array of addressable elements is a physical unclonable function.
11. The computing device of claim 9 , wherein each address in the set of addresses identifies a series of successive hardware elements in the array of addressable elements.
12. The computing device of claim 9 , wherein processing the random number to produce at least a set of addresses additionally yields at least a set of modified reading instructions configured to modify the set of reading instructions.
13. The computing device of claim 12 , wherein processing the random number to produce at least a set of addresses additionally yields at least a set of modified reading instructions configured to modify the set of reading instructions by adjusting a spacing interval between successive hardware elements in the array of addressable elements.
14. The computing device of claim 9 , wherein processing the random number to produce at least a set of addresses includes:
combining the random number with an additional identifying information to generate a first input;
executing a hash function on the first input to generate a hash digest; and
subdividing the hash digest into at least a set of addresses.
15. The computing device of claim 9 , wherein generating a set of responses further includes a preliminary step comprising:
generating a preliminary series of responses by interrogating the hardware elements in the array of addressable elements identified by the set of addresses;
referencing the preliminary series of responses to a table of modified reading instructions; and
incorporating the modified reading instructions into subsequent reading instructions.
16. The computing device of claim 9 , wherein all of the appended responses are from addressable elements that generate a predictable response when interrogated.