Interconnect structure with partial sidewall liner

1. An interconnect structure, comprising:

a substrate;

a dielectric disposed as a single layer on the substrate having at least one feature present therein, wherein the at least one feature is fully contained within the single layer of the dielectric;

a barrier layer lining the at least one feature;

a seed enhancement liner disposed over the barrier layer along sidewalls of the at least one feature, wherein the seed enhancement liner is present along only a middle portion of the sidewalls of the at least one feature; and

at least one interconnect disposed within the at least one feature over the barrier layer and the seed enhancement liner.

2. The interconnect structure of claim 1 , wherein the at least one feature is selected from the group consisting of: a trench, a via, and combinations thereof.

3. The interconnect structure of claim 1 , wherein the barrier layer comprises a material selected from the group consisting of: tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), and combinations thereof.

4. The interconnect structure of claim 1 , wherein the seed enhancement liner comprises a material selected from the group consisting of: ruthenium (Ru), rhodium (Rh), palladium (Pd), and combinations thereof.

5. The interconnect structure of claim 1 , wherein the at least one interconnect comprises copper (Cu).

6. The interconnect structure of claim 1 , wherein a top surface of the at least one interconnect is coplanar with a top surface of the dielectric.

7. The interconnect structure of claim 1 , wherein the at least one interconnect has a flanged top and bottom with the top and the bottom of the at least one interconnect having a width W 1 and a middle of the at least one interconnect having a width W 2 , and wherein W 1 >W 2 .

8. The interconnect structure of claim 1 , wherein the middle portion of the sidewalls of the at least one feature along which the seed enhancement liner is present comprises less than or equal to about 60% of a total sidewall height H of the at least one feature.

9. The interconnect structure of claim 1 , wherein the middle portion of the sidewalls of the at least one feature along which the seed enhancement liner is present comprises from about 50% to about 60% and ranges therebetween of a total sidewall height Hof the at least one feature.

10. The interconnect structure of claim 1 , wherein the at least one interconnect comprises a metal line, a conductive via or combinations thereof.

11. A method of forming an interconnect structure, the method comprising the steps of:

depositing a dielectric as a single layer onto a substrate;

patterning at least one feature in the dielectric, wherein the at least one feature is fully contained within the single layer of the dielectric;

depositing a barrier layer into and lining the at least one feature;

forming a seed enhancement liner over the barrier layer along only a middle portion of sidewalls of the at least one feature; and

forming at least one interconnect within the at least one feature over the barrier layer and the seed enhancement liner.

12. The method of claim 11 , further comprising the steps of:

depositing a first copper (Cu) fill into the at least one feature over the barrier layer;

recessing the first Cu fill to form a recessed Cu fill;

depositing a seed enhancement liner into the at least one feature over the barrier layer and the recessed Cu fill;

depositing a first Cu-containing seed layer into the at least one feature over the seed enhancement liner, the barrier layer and the recessed Cu fill;

depositing a second Cu fill into the at least one feature over the first Cu-containing seed layer;

recessing the first Cu-containing seed layer and the second Cu fill; and

recessing the seed enhancement liner such that the seed enhancement liner is absent from a top of the at least one feature.

13. The method of claim 12 , further comprising the steps of:

depositing a second Cu-containing seed layer into the at least one feature over the first Cu-containing seed layer, the second Cu fill, and the seed enhancement liner that have been recessed;

depositing a third Cu fill into the at least one feature over the second Cu-containing seed layer;

polishing the third Cu fill and the second Cu-containing seed layer, wherein the recessed Cu fill, the first Cu-containing seed layer, the second Cu fill, the second Cu-containing seed layer and the third Cu fill collectively form the at least one interconnect disposed within the at least one feature.

14. The method of claim 12 , wherein, following the polishing step, a top surface of the at least one interconnect is coplanar with a top surface of the dielectric.

15. The method of claim 11 , wherein the at least one interconnect has a flanged top and bottom with the top and the bottom of the at least one interconnect having a width W 1 and a middle of the at least one interconnect having a width W 2 , and wherein W 1 >W 2 .

16. The method of claim 11 , wherein the middle portion of the sidewalls of the at least one feature along which the seed enhancement liner is present comprises from about 50% to about 60% and ranges therebetween of a total sidewall height H of the at least one feature.

17. The method of claim 11 , wherein the at least one features is selected from the group consisting of: a trench, a via, and combinations thereof.

18. The method of claim 11 , wherein the barrier layer comprises a material selected from the group consisting of: Ta, TaN, Ti, TiN, WN, and combinations thereof.

19. The method of claim 11 , wherein the seed enhancement liner comprises a material selected from the group consisting of: Ru, Rh, Pd, and combinations thereof.