IP Library Granted Patent US 11,271,000
Granted Patent B2
US 11,271,000 · App. 16/180,010 · Granted Mar 8, 2022

Method for fabricating semiconductor device

Inventors: Bo-Ruei Cheng (Kaohsiung, TW); Li-Wei Feng (Kaohsiung, TW)
Assignees: UNITED MICROELECTRONICS CORP.; Fujian Jinhua Integrated Circuit Co., Ltd.
H01L27/10829H01L21/02238H01L21/76227H01L27/1087H01L29/0649
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Quick Facts
Patent No.
US 11,271,000
App. No.
16/180,010
Granted
Mar 8, 2022
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a first oxide layer in the trench; forming a silicon layer on the first oxide layer; performing an oxidation process to transform the silicon layer into a second oxide layer; and planarizing the second oxide layer and the first oxide layer to form a shallow trench isolation (STI).

Claims (14)

1. A method for fabricating semiconductor device, comprising:

forming a trench in a substrate;

forming a first oxide layer in the trench, wherein the first oxide layer is a single-layered structure made of silicon oxide;

forming a silicon layer on and directly contacting the first oxide layer without filling the trench completely, wherein a thickness of the silicon layer is less than a thickness of the first oxide layer;

performing an oxidation process to transform the silicon layer into a second oxide layer for filling the trench completely, wherein a maximum width of the second oxide layer in the trench is greater than a maximum width of the silicon layer in the trench; and

planarizing the second oxide layer and the first oxide layer to form a shallow trench isolation (STI).

2. The method of claim 1 , further comprising forming the silicon layer on the first oxide layer without filling the trench completely.

3. The method of claim 1 , further comprising transforming the silicon layer into the second oxide layer to fill the trench completely.

4. The method of claim 1 , further comprising performing an atomic layer deposition (ALD) process to form the first oxide layer.

5. The method of claim 1 , wherein the oxidation process comprises an in-situ steam generation (ISSG) process.

6. The method of claim 1 , wherein a thickness of the silicon layer is less than a thickness of the first oxide layer.

7. The method of claim 1 , wherein a thickness of the second oxide layer is greater than a thickness of the silicon layer.

8. The method of claim 1 , wherein the silicon layer comprises an amorphous silicon layer.

9. The method of claim 1 , wherein the first oxide layer and the second oxide layer comprise silicon oxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 5, 2018
From: CHENG, BO-RUEI; FENG, LI-WEI
To: UNITED MICROELECTRONICS CORP.; FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Reel/Frame 047407/0022 →
Priority Claims (1)
CN 201811172593.4 · Oct 9, 2018 · national
Continuity (1)
Related Publication 20200111794A1 · Apr 9, 2020
Cited By (1)
US 12,426,296